diff --git a/.cproject b/.cproject index d225ac3..856c3b1 100644 --- a/.cproject +++ b/.cproject @@ -14,4 +14,5 @@ - \ No newline at end of file + + diff --git a/components/custom_board/CMakeLists.txt b/components/custom_board/CMakeLists.txt index 5a1d737..5420353 100644 --- a/components/custom_board/CMakeLists.txt +++ b/components/custom_board/CMakeLists.txt @@ -10,6 +10,12 @@ if(CONFIG_AUDIO_BOARD_CUSTOM) ./generic_board/board_pins_config.c ) + if (CONFIG_DAC_ADAU1961) + message(STATUS "Selected DAC is " CONFIG_DAC_ADAU1961) + list(APPEND COMPONENT_ADD_INCLUDEDIRS ./adau1961/include) + list(APPEND COMPONENT_SRCS ./adau1961/adau1961.c) + endif() + if(CONFIG_DAC_PCM51XX) message(STATUS "Selected DAC is " CONFIG_DAC_PCM15XX) list(APPEND COMPONENT_ADD_INCLUDEDIRS ./pcm51xx/include) diff --git a/components/custom_board/Kconfig.projbuild b/components/custom_board/Kconfig.projbuild index ae2b159..1d49ed0 100644 --- a/components/custom_board/Kconfig.projbuild +++ b/components/custom_board/Kconfig.projbuild @@ -19,6 +19,8 @@ menu "Custom Audio Board" config DAC_MA120X0 bool "Infineon MA120X0 ClassD AMP" + config DAC_ADAU1961 + bool "Analog Devices ADAU1961 DAC" endchoice @@ -41,6 +43,12 @@ menu "Custom Audio Board" endmenu menu "I2S master interface" + config MASTER_I2S_MCLK_PIN + int "Master i2s mclk" + default 0 + help + Master audio interface master clock. + config MASTER_I2S_BCK_PIN int "Master i2s bck" default 23 @@ -61,7 +69,6 @@ menu "Custom Audio Board" endmenu menu "I2S slave interface" - config SLAVE_I2S_BCK_PIN int "Slave i2s bck" default 26 diff --git a/components/custom_board/adau1961/adau1961.c b/components/custom_board/adau1961/adau1961.c new file mode 100644 index 0000000..0f9679a --- /dev/null +++ b/components/custom_board/adau1961/adau1961.c @@ -0,0 +1,606 @@ +/* + * TI ADAU1961 audio hal + * + * Mostly stubs (no I2C or volume control) + * Configuration of mute/unmute gpio in init (connected to XSMT) + */ + +#include "adau1961.h" +#include "adau1962_reg_addr.h" + +#include +#include +#include "board.h" +#include "esp_log.h" + +#include "i2c_bus.h" + +typedef struct adau1961_cfg_reg_s { + uint16_t address; + uint8_t value; +} adau1961_cfg_reg_t; + +static const char *TAG = "ADAU1961"; + +#define ADAU1961_ASSERT(a, format, b, ...) \ + if ((a) != 0) { \ + ESP_LOGE(TAG, format, ##__VA_ARGS__); \ + return b; \ + } + +static i2c_bus_handle_t i2c_handler = NULL; + +static const int adau1961_addr = CONFIG_DAC_I2C_ADDR; + +// adau1961_cfg_reg_t + +/* + * i2c default configuration + */ +static i2c_config_t i2c_cfg = { + .mode = I2C_MODE_MASTER, + .sda_pullup_en = GPIO_PULLUP_DISABLE, + .scl_pullup_en = GPIO_PULLUP_DISABLE, + .master.clk_speed = 400000, +}; + +esp_err_t adau1961_ctrl(audio_hal_codec_mode_t mode, + audio_hal_ctrl_t ctrl_state); + +esp_err_t adau1961_config_iface(audio_hal_codec_mode_t mode, + audio_hal_codec_i2s_iface_t *iface); + +/* + * Operate function + */ +audio_hal_func_t AUDIO_CODEC_ADAU1961_DEFAULT_HANDLE = { + .audio_codec_initialize = adau1961_init, + .audio_codec_deinitialize = adau1961_deinit, + .audio_codec_ctrl = adau1961_ctrl, + .audio_codec_config_iface = adau1961_config_iface, + .audio_codec_set_mute = adau1961_set_mute, + .audio_codec_set_volume = adau1961_set_volume, + .audio_codec_get_volume = adau1961_get_volume, + .audio_hal_lock = NULL, + .handle = NULL, +}; + +// static esp_err_t adau1961_transmit_registers(const adau1961_cfg_reg_t +// *conf_buf, +// int size) { +// int i = 0; +// esp_err_t ret = ESP_OK; +// while (i < size) { +// ret = i2c_bus_write_bytes(i2c_handler, adau1961_addr, +// (unsigned char *)(&conf_buf[i].offset), 1, +// (unsigned char *)(&conf_buf[i].value), 1); +// i++; +// } +// if (ret != ESP_OK) { +// ESP_LOGE(TAG, "Fail to load configuration to adau1961"); +// return ESP_FAIL; +// } +// ESP_LOGI(TAG, "%s: write %d reg done", __FUNCTION__, i); +// return ret; +//} + +esp_err_t adau1961_init(audio_hal_codec_config_t *codec_cfg) { + esp_err_t ret = ESP_OK; + uint8_t data[3]; + uint8_t verify = 0; + uint8_t regContent; + + ESP_LOGI(TAG, "Power ON CODEC"); + + // TODO: configure pins through menuconfig + gpio_config_t cfg = {.pin_bit_mask = BIT64(GPIO_NUM_39) | BIT64(GPIO_NUM_34), + .mode = GPIO_MODE_DEF_INPUT, + .pull_up_en = GPIO_PULLUP_DISABLE, + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .intr_type = GPIO_INTR_DISABLE}; + gpio_config(&cfg); + + ret = get_i2c_pins(I2C_NUM_0, &i2c_cfg); + i2c_handler = i2c_bus_create(I2C_NUM_0, &i2c_cfg); + if (i2c_handler == NULL) { + ESP_LOGW(TAG, "failed to create i2c bus handler\n"); + return ESP_FAIL; + } + + ESP_LOGI(TAG, "Looking for a adau1961 chip at address 0x%x", adau1961_addr); + // set clock + data[0] = (uint8_t)(R0_CLOCK_CTRL >> 8); + data[1] = (uint8_t)R0_CLOCK_CTRL; + data[2] = 0x01; // core clock enable, 256 × f_s + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + if (ret == ESP_OK) { + ESP_LOGI(TAG, "Found a adau1961 chip at address 0x%x", adau1961_addr); + } + ADAU1961_ASSERT(ret, "Fail to detect adau1961 DAC", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R0_CLOCK_CTRL >> 8); + data[1] = (uint8_t)R0_CLOCK_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R0_CLOCK_CTRL", ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R0_CLOCK_CTRL failed, got %d", data[2]); + } + } + + // enable both DACs + data[0] = (uint8_t)(R36_DAC_CTRL0 >> 8); + data[1] = (uint8_t)R36_DAC_CTRL0; + data[2] = 0x03; + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R36_DAC_CTRL0", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R36_DAC_CTRL0 >> 8); + data[1] = (uint8_t)R36_DAC_CTRL0; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R36_DAC_CTRL0", ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R36_DAC_CTRL0 failed, got %d", data[2]); + } + } + + // enable mixer 3 and unmute left DAC input + data[0] = (uint8_t)(R22_PLAYBACK_MIXER3_LEFT_CTRL0 >> 8); + data[1] = (uint8_t)R22_PLAYBACK_MIXER3_LEFT_CTRL0; + data[2] = (1 << 5) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R22_PLAYBACK_MIXER3_LEFT_CTRL0", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R22_PLAYBACK_MIXER3_LEFT_CTRL0 >> 8); + data[1] = (uint8_t)R22_PLAYBACK_MIXER3_LEFT_CTRL0; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R22_PLAYBACK_MIXER3_LEFT_CTRL0", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R22_PLAYBACK_MIXER3_LEFT_CTRL0 failed, got %d", + data[2]); + } + } + + // enable mixer 4 and unmute right DAC input + data[0] = (uint8_t)(R24_PLAYBACK_MIXER4_RIGHT_CTRL0 >> 8); + data[1] = (uint8_t)R24_PLAYBACK_MIXER4_RIGHT_CTRL0; + data[2] = (1 << 6) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R24_PLAYBACK_MIXER4_RIGHT_CTRL0", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R24_PLAYBACK_MIXER4_RIGHT_CTRL0 >> 8); + data[1] = (uint8_t)R24_PLAYBACK_MIXER4_RIGHT_CTRL0; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R24_PLAYBACK_MIXER4_RIGHT_CTRL0", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R24_PLAYBACK_MIXER4_RIGHT_CTRL0 failed, got %d", + data[2]); + } + } + + //#if HEADPHONE_MODE + // configure headphone in capless mode + + // enable mixer 7, common mode output + data[0] = (uint8_t)(R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL; + data[2] = (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL", + ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, + "verify R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL failed, got %d", + data[2]); + } + } + + // headphone output, unmute mono output + data[0] = (uint8_t)(R33_PLAYBACK_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R33_PLAYBACK_MONO_OUT_CTRL; + data[2] = (1 << 1) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R33_PLAYBACK_MONO_OUT_CTRL", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R33_PLAYBACK_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R33_PLAYBACK_MONO_OUT_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R33_PLAYBACK_MONO_OUT_CTRL", ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R33_PLAYBACK_MONO_OUT_CTRL failed, got %d", + data[2]); + } + } + + // unmute left headphone output, set volume to 6 dB, enable headphone output + data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + data[2] = (0 << 2) | (1 << 1) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R29_PLAYBACK_HP_LEFT_VOL_CTRL", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R29_PLAYBACK_HP_LEFT_VOL_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R29_PLAYBACK_HP_LEFT_VOL_CTRL failed, got %d", + data[2]); + } + } + + // unmute right headphone output, set volume to 6 dB, enable headphone output + data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + data[2] = (0 << 2) | (1 << 1) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R30_PLAYBACK_HP_RIGHT_VOL_CTRL", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R30_PLAYBACK_HP_RIGHT_VOL_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R30_PLAYBACK_HP_RIGHT_VOL_CTRL failed, got %d", + data[2]); + } + } + + // mixer 5 enable, The signal from the left channel playback mixer (Mixer 3) + // can be enabled and boosted in the playback L/R mixer left (Mixer 5). + data[0] = (uint8_t)(R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL >> 8); + data[1] = (uint8_t)R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL; + data[2] = (2 << 1) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL", + ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL >> 8); + data[1] = (uint8_t)R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, + "Fail to read R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE( + TAG, + "verify R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL failed, got %d", + data[2]); + } + } + + // mixer 6 enable, The signal from the right channel playback mixer (Mixer 4) + // can be enabled and boosted in the playback L/R mixer right (Mixer 6). + data[0] = (uint8_t)(R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL >> 8); + data[1] = (uint8_t)R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL; + data[2] = (2 << 3) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL", + ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL >> 8); + data[1] = (uint8_t)R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, + "Fail to read R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE( + TAG, + "verify R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL failed, got %d", + data[2]); + } + } + + // // mute left headphone output, disable headphone output + // data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + // data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + // data[2] = 0x00; + // regContent = data[2]; + // ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + // ADAU1961_ASSERT(ret, "Fail to set R29_PLAYBACK_HP_LEFT_VOL_CTRL", + // ESP_FAIL); if (verify) { + // data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + // data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + // ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, + // &data[2], 1); ADAU1961_ASSERT(ret, "Fail to read + // R29_PLAYBACK_HP_LEFT_VOL_CTRL", ESP_FAIL); if (data[2] != regContent) { + // ESP_LOGE(TAG, "verify R29_PLAYBACK_HP_LEFT_VOL_CTRL failed, got %d", + // data[2]); + // } + // } + // + // // mute right headphone output, disable headphone output + // data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + // data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + // data[2] = 0x00; + // regContent = data[2]; + // ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + // ADAU1961_ASSERT(ret, "Fail to set R30_PLAYBACK_HP_RIGHT_VOL_CTRL", + // ESP_FAIL); if (verify) { + // data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + // data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + // ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, + // &data[2], 1); ADAU1961_ASSERT(ret, "Fail to read + // R30_PLAYBACK_HP_RIGHT_VOL_CTRL", ESP_FAIL); if (data[2] != regContent) { + // ESP_LOGE(TAG, "verify R30_PLAYBACK_HP_RIGHT_VOL_CTRL failed, got %d", + // data[2]); + // } + // } + + // unmute left line out channel, volume 0dB + data[0] = (uint8_t)(R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL; + data[2] = (0 << 2) | (1 << 1); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL", + ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL failed, got %d", + data[2]); + } + } + + // unmute right line out channel, volume 0dB + data[0] = (uint8_t)(R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL; + data[2] = (0 << 2) | (1 << 1); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL", + ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL", + ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, + "verify R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL failed, got %d", + data[2]); + } + } + + // line output, mute mono output + data[0] = (uint8_t)(R33_PLAYBACK_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R33_PLAYBACK_MONO_OUT_CTRL; + data[2] = 0x00; + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R33_PLAYBACK_MONO_OUT_CTRL", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R33_PLAYBACK_MONO_OUT_CTRL >> 8); + data[1] = (uint8_t)R33_PLAYBACK_MONO_OUT_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R33_PLAYBACK_MONO_OUT_CTRL", ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R33_PLAYBACK_MONO_OUT_CTRL failed, got %d", + data[2]); + } + } + + // Playback right and left channel enable + data[0] = (uint8_t)(R35_PLAYBACK_PWR_MGMT >> 8); + data[1] = (uint8_t)R35_PLAYBACK_PWR_MGMT; + data[2] = (1 << 1) | (1 << 0); + regContent = data[2]; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R35_PLAYBACK_PWR_MGMT", ESP_FAIL); + if (verify) { + data[0] = (uint8_t)(R35_PLAYBACK_PWR_MGMT >> 8); + data[1] = (uint8_t)R35_PLAYBACK_PWR_MGMT; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); + ADAU1961_ASSERT(ret, "Fail to read R35_PLAYBACK_PWR_MGMT", ESP_FAIL); + if (data[2] != regContent) { + ESP_LOGE(TAG, "verify R35_PLAYBACK_PWR_MGMT failed, got %d", data[2]); + } + } + + return ret; +} + +esp_err_t adau1961_get_volume(int *vol) { + esp_err_t ret = ESP_OK; + uint8_t data[3]; + int8_t volIndB; + + // get current register setting of left channel + data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R29_PLAYBACK_HP_LEFT_VOL_CTRL", ESP_FAIL); + + // volIndB = ((data[2] >> 2) & 0x3F) - 57; + //*vol = pow(10, ((float)volIndB / 20.0)) * 50.0; + + volIndB = ((data[2] >> 2) & 0x3F); + *vol = (int)volIndB * 100 / 63; + + // we assume all channel are set to the same volume. + // this is a save assumption, as we are setting them in + // adau1961_set_volume() + + /* + // get current register setting of right channel + data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); ADAU1961_ASSERT(ret, "Fail to read R30_PLAYBACK_HP_RIGHT_VOL_CTRL", + ESP_FAIL); + + // get current register setting of line left channel + data[0] = (uint8_t)(R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); ADAU1961_ASSERT(ret, "Fail to read R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL", + ESP_FAIL); + + // get current register setting of line right channel + data[0] = (uint8_t)(R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL; + ret = i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], + 1); ADAU1961_ASSERT(ret, "Fail to read R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL", + ESP_FAIL); + */ + + return ret; +} + +esp_err_t adau1961_set_volume(int vol) { + esp_err_t ret = ESP_OK; + uint8_t data[3]; + uint8_t volIndB; + + volIndB = ceil((63.0 * (float)vol) / 100.0); + if (volIndB > 63) { + volIndB = 63; + } + + // if (vol == 0) { + // volIndB = 20 * log10(0.07/50.0) + 57.0; + // } + // else { + // if (vol > 100) { + // vol = 100; + // } + // + // volIndB = 20.0 * log10(vol/50.0) + 57.0; + // } + + // get current register setting of HP left channel + data[0] = (uint8_t)(R29_PLAYBACK_HP_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R29_PLAYBACK_HP_LEFT_VOL_CTRL; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R29_PLAYBACK_HP_LEFT_VOL_CTRL", ESP_FAIL); + data[2] &= ~(0x3F << 2); + data[2] |= ((uint8_t)volIndB) << 2; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R29_PLAYBACK_HP_LEFT_VOL_CTRL", ESP_FAIL); + + // get current register setting of HP right channel + data[0] = (uint8_t)(R30_PLAYBACK_HP_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R30_PLAYBACK_HP_RIGHT_VOL_CTRL; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R30_PLAYBACK_HP_RIGHT_VOL_CTRL", ESP_FAIL); + data[2] &= ~(0x3F << 2); + data[2] |= ((uint8_t)volIndB) << 2; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + + // get current register setting of line left channel + data[0] = (uint8_t)(R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL >> 8); + data[1] = (uint8_t)R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL", + ESP_FAIL); + data[2] &= ~(0x3F << 2); + data[2] |= ((uint8_t)volIndB) << 2; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL", + ESP_FAIL); + + // get current register setting of line right channel + data[0] = (uint8_t)(R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL >> 8); + data[1] = (uint8_t)R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL", + ESP_FAIL); + data[2] &= ~(0x3F << 2); + data[2] |= ((uint8_t)volIndB) << 2; + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to set R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL", + ESP_FAIL); + + return ret; +} + +esp_err_t adau1961_set_mute(bool enable) { + esp_err_t ret = ESP_OK; + uint8_t data[3]; + + // Playback right and left channel enable + data[0] = (uint8_t)(R35_PLAYBACK_PWR_MGMT >> 8); + data[1] = (uint8_t)R35_PLAYBACK_PWR_MGMT; + data[2] = (!enable << 1) | (!enable << 0); + ret = i2c_bus_write_data(i2c_handler, adau1961_addr, data, 3); + ADAU1961_ASSERT(ret, "Fail to write R35_PLAYBACK_PWR_MGMT", ESP_FAIL); + + return ret; +} + +esp_err_t adau1961_get_mute(bool *enabled) { + esp_err_t ret = ESP_OK; + uint8_t data[3]; + + data[0] = (uint8_t)(R35_PLAYBACK_PWR_MGMT >> 8); + data[1] = (uint8_t)R35_PLAYBACK_PWR_MGMT; + ret = + i2c_bus_read_bytes(i2c_handler, adau1961_addr, &data[0], 2, &data[2], 1); + ADAU1961_ASSERT(ret, "Fail to read R35_PLAYBACK_PWR_MGMT", ESP_FAIL); + + *enabled = ((data[2] & 0x03) == 0); + + return ret; +} + +esp_err_t adau1961_deinit(void) { + // TODO + return ESP_OK; +} + +esp_err_t adau1961_ctrl(audio_hal_codec_mode_t mode, + audio_hal_ctrl_t ctrl_state) { + // TODO + return ESP_OK; +} + +esp_err_t adau1961_config_iface(audio_hal_codec_mode_t mode, + audio_hal_codec_i2s_iface_t *iface) { + // TODO + return ESP_OK; +} diff --git a/components/custom_board/adau1961/include/adau1961.h b/components/custom_board/adau1961/include/adau1961.h new file mode 100644 index 0000000..88f72d2 --- /dev/null +++ b/components/custom_board/adau1961/include/adau1961.h @@ -0,0 +1,49 @@ +/* + * ANALOG adau1961 audio hal + */ + +#ifndef _ADAU1961_H_ +#define _ADAU1961_H_ + +#include "audio_hal.h" +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize adau1961 codec chip + */ +esp_err_t adau1961_init(audio_hal_codec_config_t *codec_cfg); + +/** + * Deinitialize adau1961 codec chip + */ +esp_err_t adau1961_deinit(void); + +/** + * Set volume - NOT AVAILABLE + */ +esp_err_t adau1961_set_volume(int vol); + +/** + * Get volume - NOT AVAILABLE + */ +esp_err_t adau1961_get_volume(int *vol); + +/** + * Set adau1961 mute or not + */ +esp_err_t adau1961_set_mute(bool enable); + +/** + * Get adau1961 mute status - NOT IMPLEMENTED + */ +esp_err_t adau1961_get_mute(bool *enabled); + +#ifdef __cplusplus +} +#endif + +#endif // _ADAU1961_H_ diff --git a/components/custom_board/adau1961/include/adau1962_reg_addr.h b/components/custom_board/adau1961/include/adau1962_reg_addr.h new file mode 100644 index 0000000..d1550a0 --- /dev/null +++ b/components/custom_board/adau1961/include/adau1962_reg_addr.h @@ -0,0 +1,54 @@ +/* + * ANALOG adau1961 register address definitions + */ + +#ifndef _ADAU1961_REG_ADDR_H_ +#define _ADAU1961_REG_ADDR_H_ + +enum { + R0_CLOCK_CTRL = 0x4000, + R1_PLL_CLOCK_CTRL = 0x4002, + R2_DIGITAL_MIC_OR_JACK_DET_CTRL = 0x4008, + R4_RECORD_MIXER1_LEFT_CTRL0 = 0x400A, + R5_RECORD_MIXER1_LEFT_CTRL1 = 0x400B, + R6_RECORD_MIXER2_RIGHT_CTRL0 = 0x400C, + R7_RECORD_MIXER2_RIGHT_CTRL1 = 0x400D, + R8_LEFT_DIFF_IN_VOL_CTRL = 0x400E, + R9_RIGHT_DIFF_IN_VOL_CTRL = 0x400F, + R10_REC_MIC_BIAS_CTRL = 0x4010, + R11_ALC_CTRL0 = 0x4011, + R12_ALC_CTRL1 = 0x4012, + R13_ALC_CTRL2 = 0x4013, + R14_ALC_CTRL3 = 0x4014, + R15_SERIAL_PORT_CTRL0 = 0x4015, + R16_SERIAL_PORT_CTRL1 = 0x4016, + R17_SERIAL_CONV_CTRL0 = 0x4017, + R18_SERIAL_CONV_CTRL1 = 0x4018, + R19_ADC_CTRL = 0x4019, + R20_LEFT_IN_DIG_VOL_CTRL = 0x401A, + R21_RIGHT_IN_DIG_VOL_CTRL = 0x401B, + R22_PLAYBACK_MIXER3_LEFT_CTRL0 = 0x401C, + R23_PLAYBACK_MIXER3_LEFT_CTRL1 = 0x401D, + R24_PLAYBACK_MIXER4_RIGHT_CTRL0 = 0x401E, + R25_PLAYBACK_MIXER4_RIGHT_CTRL1 = 0x401F, + R26_PLAYBACK_LR_MIXER5_LEFT_LINE_OUT_CTRL = 0x4020, + R27_PLAYBACK_LR_MIXER6_RIGHT_LINE_OUT_CTRL = 0x4021, + R28_PLAYBACK_LR_MIXER7_MONO_OUT_CTRL = 0x4022, + R29_PLAYBACK_HP_LEFT_VOL_CTRL = 0x4023, + R30_PLAYBACK_HP_RIGHT_VOL_CTRL = 0x4024, + R31_PLAYBACK_LINE_OUT_LEFT_VOL_CTRL = 0x4025, + R32_PLAYBACK_LINE_OUT_RIGHT_VOL_CTRL = 0x4026, + R33_PLAYBACK_MONO_OUT_CTRL = 0x4027, + R34_PLAYBACK_POP_CLICK_SUP = 0x4028, + R35_PLAYBACK_PWR_MGMT = 0x4029, + R36_DAC_CTRL0 = 0x402A, + R37_DAC_CTRL1 = 0x402B, + R38_DAC_CTRL2 = 0x402C, + R39_SERIAL_PORT_PAD_CTRL = 0x402D, + R40_CTRL_PORT_PAD_CTRL0 = 0x402F, + R41_CTRL_PORT_PAD_CTRL1 = 0x4030, + R42_JACK_DET_PIN_CTRL = 0x4031, + R43_DEJITTER_CTRL = 0x4036, +}; + +#endif // _ADAU1961_REG_ADDR_H_ diff --git a/components/custom_board/generic_board/board.c b/components/custom_board/generic_board/board.c index ea6865a..11b0066 100644 --- a/components/custom_board/generic_board/board.c +++ b/components/custom_board/generic_board/board.c @@ -43,39 +43,37 @@ extern audio_hal_func_t AUDIO_CODEC_MA120X0_DEFAULT_HANDLE; #elif CONFIG_DAC_MA120 extern audio_hal_func_t AUDIO_CODEC_MA120_DEFAULT_HANDLE; #define AUDIO_CODEC_DEFAULT_HANDLE AUDIO_CODEC_MA120_DEFAULT_HANDLE +#elif CONFIG_DAC_ADAU1961 +extern audio_hal_func_t AUDIO_CODEC_ADAU1961_DEFAULT_HANDLE; +#define AUDIO_CODEC_DEFAULT_HANDLE AUDIO_CODEC_ADAU1961_DEFAULT_HANDLE #endif static const char *TAG = "AUDIO_BOARD"; static audio_board_handle_t board_handle = 0; -audio_board_handle_t -audio_board_init (void) -{ - if (board_handle) - { - ESP_LOGW (TAG, "The board has already been initialized!"); - return board_handle; - } - board_handle = (audio_board_handle_t)audio_calloc ( - 1, sizeof (struct audio_board_handle)); - AUDIO_MEM_CHECK (TAG, board_handle, return NULL); - board_handle->audio_hal = audio_board_codec_init (); - ESP_LOGI (TAG, "board-handle done"); +audio_board_handle_t audio_board_init(void) { + if (board_handle) { + ESP_LOGW(TAG, "The board has already been initialized!"); + return board_handle; + } + board_handle = + (audio_board_handle_t)audio_calloc(1, sizeof(struct audio_board_handle)); + AUDIO_MEM_CHECK(TAG, board_handle, return NULL); + board_handle->audio_hal = audio_board_codec_init(); + ESP_LOGI(TAG, "board-handle done"); return board_handle; } -audio_hal_handle_t -audio_board_codec_init (void) -{ - ESP_LOGI ("HAL", "INIT"); - audio_hal_codec_config_t audio_codec_cfg = AUDIO_CODEC_DEFAULT_CONFIG (); +audio_hal_handle_t audio_board_codec_init(void) { + ESP_LOGI("HAL", "INIT"); + audio_hal_codec_config_t audio_codec_cfg = AUDIO_CODEC_DEFAULT_CONFIG(); - audio_hal_handle_t codec_hal - = audio_hal_init (&audio_codec_cfg, &AUDIO_CODEC_DEFAULT_HANDLE); - ESP_LOGI ("HAL", "codec_hal done"); + audio_hal_handle_t codec_hal = + audio_hal_init(&audio_codec_cfg, &AUDIO_CODEC_DEFAULT_HANDLE); + ESP_LOGI("HAL", "codec_hal done"); - AUDIO_NULL_CHECK (TAG, codec_hal, return NULL); + AUDIO_NULL_CHECK(TAG, codec_hal, return NULL); return codec_hal; } @@ -109,18 +107,12 @@ audio_board_codec_init (void) // return ret; //} -audio_board_handle_t -audio_board_get_handle (void) -{ - return board_handle; -} +audio_board_handle_t audio_board_get_handle(void) { return board_handle; } -esp_err_t -audio_board_deinit (audio_board_handle_t audio_board) -{ +esp_err_t audio_board_deinit(audio_board_handle_t audio_board) { esp_err_t ret = ESP_OK; - ret |= audio_hal_deinit (audio_board->audio_hal); - free (audio_board); + ret |= audio_hal_deinit(audio_board->audio_hal); + free(audio_board); board_handle = NULL; return ret; } diff --git a/components/lightsnapcast/player.c b/components/lightsnapcast/player.c index 737f4a8..12ae4f7 100644 --- a/components/lightsnapcast/player.c +++ b/components/lightsnapcast/player.c @@ -170,6 +170,8 @@ static esp_err_t player_setup_i2s(i2s_port_t i2sNum, i2s_custom_driver_install(i2sNum, &i2s_config0, 0, NULL); i2s_custom_set_pin(i2sNum, &pin_config0); + i2s_mclk_gpio_select(i2sNum, CONFIG_MASTER_I2S_MCLK_PIN); + return 0; } @@ -1319,8 +1321,8 @@ static void player_task(void *pvParameters) { const bool enableControlLoop = true; - const int64_t shortOffset = 2; // 8; // 20; //µs, softsync - const int64_t miniOffset = 1; //µs, softsync + const int64_t shortOffset = 2; //µs, softsync + const int64_t miniOffset = 1; //µs, softsync const int64_t hardResyncThreshold = 10000; //µs, hard sync if (initialSync == 1) { @@ -1331,11 +1333,12 @@ static void player_task(void *pvParameters) { shortMedian = MEDIANFILTER_Insert(&shortMedianFilter, avg); miniMedian = MEDIANFILTER_Insert(&miniMedianFilter, avg); - // resync if we are getting late. + // resync if we are getting very late / early. // hopefully being early will get ok // through apll speed control if ((uxQueueMessagesWaiting(pcmChkQHdl) == 0) || - (abs(avg) > hardResyncThreshold)) { + ((abs(avg) > hardResyncThreshold) && + MEDIANFILTER_isFull(&shortMedianFilter))) { if (chnk != NULL) { free_pcm_chunk(chnk); chnk = NULL; diff --git a/components/ui_http_server/Kconfig.projbuild b/components/ui_http_server/Kconfig.projbuild deleted file mode 100644 index 0f48900..0000000 --- a/components/ui_http_server/Kconfig.projbuild +++ /dev/null @@ -1,32 +0,0 @@ -menu "Application Configuration" - - menu "HTTP Server Setting" - - config WEB_PORT - int "HTTP Server Port" - default 8000 - help - HTTP server port to use. - - endmenu - - menu "GPIO Setting" - - config GPIO_RANGE_MAX - int - default 33 if IDF_TARGET_ESP32 - default 46 if IDF_TARGET_ESP32S2 - default 48 if IDF_TARGET_ESP32S3 - default 19 if IDF_TARGET_ESP32C3 - - config BLINK_GPIO - int "Blink GPIO number" - range 0 GPIO_RANGE_MAX - default 5 - help - GPIO number (IOxx) to blink on and off or the RMT signal for the addressable LED. - Some GPIOs are used for other purposes (flash connections, etc.) and cannot be used to blink. - - endmenu - -endmenu diff --git a/main/Kconfig.projbuild b/main/Kconfig.projbuild index f8fc769..6d925db 100644 --- a/main/Kconfig.projbuild +++ b/main/Kconfig.projbuild @@ -25,4 +25,15 @@ menu "Snapcast Configuration" default "ESP32-Caster" help Name of the client to register the snapserver. + + menu "HTTP Server Setting" + + config WEB_PORT + int "User interface HTTP Server Port" + default 8000 + help + HTTP server port to use. + + endmenu + endmenu diff --git a/main/main.c b/main/main.c index 6d8a757..b32f3d2 100644 --- a/main/main.c +++ b/main/main.c @@ -470,6 +470,17 @@ static void flac_decoder_task(void *pvParameters) { FLAC__StreamDecoderInitStatus init_status; snapcastSetting_t *scSet = (snapcastSetting_t *)pvParameters; + if (flacTaskQHdl != NULL) { + vQueueDelete(flacTaskQHdl); + flacTaskQHdl = NULL; + } + + flacTaskQHdl = xQueueCreate(8, sizeof(flacData_t *)); + if (flacTaskQHdl == NULL) { + ESP_LOGE(TAG, "Failed to create flac flacTaskQHdl"); + return; + } + if (decoderReadQHdl != NULL) { vQueueDelete(decoderReadQHdl); decoderReadQHdl = NULL; @@ -532,17 +543,6 @@ void flac_task(void *pvParameters) { int flow_drain_counter = 0; #endif - if (flacTaskQHdl != NULL) { - vQueueDelete(flacTaskQHdl); - flacTaskQHdl = NULL; - } - - flacTaskQHdl = xQueueCreate(8, sizeof(flacData_t *)); - if (flacTaskQHdl == NULL) { - ESP_LOGE(TAG, "Failed to create flac flacTaskQHdl"); - return; - } - while (1) { xQueueReceive(flacTaskQHdl, &pFlacData, portMAX_DELAY); // get data from tcp task @@ -643,7 +643,13 @@ void flac_task(void *pvParameters) { * */ esp_err_t audio_set_mute(bool mute) { - return audio_hal_set_mute(board_handle->audio_hal, mute); + if (!board_handle) { + ESP_LOGW(TAG, "audio board not initialized yet"); + + return ESP_OK; + } else { + return audio_hal_set_mute(board_handle->audio_hal, mute); + } } /** @@ -1984,6 +1990,13 @@ static void http_get_task(void *pvParameters) { FLAC_DECODER_TASK_CORE_ID); } + // TODO: find a smarter way for + // this wait for task creation done + // maybe use task notification + while (flacTaskQHdl == NULL) { + vTaskDelay(10); + } + #if TEST_DECODER_TASK if (t_flac_task == NULL) { xTaskCreatePinnedToCore( @@ -2001,13 +2014,6 @@ static void http_get_task(void *pvParameters) { pFlacData->outData = NULL; pFlacData->type = SNAPCAST_MESSAGE_CODEC_HEADER; - // TODO: find a smarter way for - // this wait for task creation done - // maybe use task notification - while (flacTaskQHdl == NULL) { - vTaskDelay(10); - } - // ESP_LOGE(TAG, "%s: flacTaskQHdl start codec // header", __func__); @@ -2666,6 +2672,28 @@ void app_main(void) { esp_timer_init(); + // some codecs need i2s mclk for initialization + i2s_config_t i2s_config0 = { + .mode = I2S_MODE_MASTER | I2S_MODE_TX, // Only TX + .sample_rate = 44100, + .bits_per_sample = 16, + .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, // 2-channels + .communication_format = I2S_COMM_FORMAT_STAND_I2S, + .dma_buf_count = 2, + .dma_buf_len = 128, + .intr_alloc_flags = 1, // Default interrupt priority + .use_apll = true, + .fixed_mclk = 0, + .tx_desc_auto_clear = true // Auto clear tx descriptor on underflow + }; + i2s_pin_config_t pin_config0; + get_i2s_pins(I2S_NUM_0, &pin_config0); + + i2s_custom_driver_uninstall(I2S_NUM_0); + i2s_custom_driver_install(I2S_NUM_0, &i2s_config0, 0, NULL); + i2s_custom_set_pin(I2S_NUM_0, &pin_config0); + i2s_mclk_gpio_select(I2S_NUM_0, CONFIG_MASTER_I2S_MCLK_PIN); + ESP_LOGI(TAG, "Start codec chip"); board_handle = audio_board_init(); ESP_LOGI(TAG, "Audio board_init done"); @@ -2674,11 +2702,10 @@ void app_main(void) { AUDIO_HAL_CTRL_START); audio_hal_set_mute(board_handle->audio_hal, true); // ensure no noise is sent after firmware crash - i2s_mclk_gpio_select(0, 0); - // setup_ma120(); ESP_LOGI(TAG, "init player"); init_player(); + // setup_ma120(); // Enable and setup WIFI in station mode and connect to Access point setup in // menu config or set up provisioning mode settable in menuconfig diff --git a/sdkconfig b/sdkconfig index ccb8dee..b8c11b5 100644 --- a/sdkconfig +++ b/sdkconfig @@ -130,8 +130,8 @@ CONFIG_PARTITION_TABLE_MD5=y # # Audio HAL # -# CONFIG_AUDIO_BOARD_CUSTOM is not set -CONFIG_ESP_LYRAT_V4_3_BOARD=y +CONFIG_AUDIO_BOARD_CUSTOM=y +# CONFIG_ESP_LYRAT_V4_3_BOARD is not set # CONFIG_ESP_LYRAT_V4_2_BOARD is not set # CONFIG_ESP_LYRATD_MSC_V2_1_BOARD is not set # CONFIG_ESP_LYRATD_MSC_V2_2_BOARD is not set @@ -140,6 +140,41 @@ CONFIG_ESP_LYRAT_V4_3_BOARD=y # CONFIG_ESP32_S2_KALUGA_1_V1_2_BOARD is not set # end of Audio HAL +# +# Custom Audio Board +# +# CONFIG_DAC_PCM51XX is not set +# CONFIG_DAC_PCM5102A is not set +# CONFIG_DAC_MA120 is not set +# CONFIG_DAC_MA120X0 is not set +CONFIG_DAC_ADAU1961=y + +# +# DAC I2C control interface +# +CONFIG_DAC_I2C_SDA=12 +CONFIG_DAC_I2C_SCL=14 +CONFIG_DAC_I2C_ADDR=0x70 +# end of DAC I2C control interface + +# +# I2S master interface +# +CONFIG_MASTER_I2S_MCLK_PIN=3 +CONFIG_MASTER_I2S_BCK_PIN=15 +CONFIG_MASTER_I2S_LRCK_PIN=13 +CONFIG_MASTER_I2S_DATAOUT_PIN=4 +# end of I2S master interface + +# +# I2S slave interface +# +CONFIG_SLAVE_I2S_BCK_PIN=26 +CONFIG_SLAVE_I2S_LRCK_PIN=12 +CONFIG_SLAVE_I2S_DATAOUT_PIN=5 +# end of I2S slave interface +# end of Custom Audio Board + # # ESP32 DSP processor config # @@ -159,24 +194,6 @@ CONFIG_SNTP_TIMEZONE="UTC" CONFIG_SNTP_SERVER="pool.ntp.org" # end of SNTP Configuration -# -# Application Configuration -# - -# -# HTTP Server Setting -# -CONFIG_WEB_PORT=8000 -# end of HTTP Server Setting - -# -# GPIO Setting -# -CONFIG_GPIO_RANGE_MAX=33 -CONFIG_BLINK_GPIO=5 -# end of GPIO Setting -# end of Application Configuration - # # Wifi Configuration # @@ -189,6 +206,12 @@ CONFIG_WIFI_MAXIMUM_RETRY=0 # CONFIG_SNAPSERVER_USE_MDNS=y CONFIG_SNAPCLIENT_NAME="esp-snapclient" + +# +# HTTP Server Setting +# +CONFIG_WEB_PORT=8000 +# end of HTTP Server Setting # end of Snapcast Configuration # @@ -413,7 +436,7 @@ CONFIG_ADC_CAL_LUT_ENABLE=y CONFIG_ESP_ERR_TO_NAME_LOOKUP=y CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_ESP_MAIN_TASK_STACK_SIZE=2048 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=2560 CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 @@ -1290,7 +1313,7 @@ CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y # CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_MAIN_TASK_STACK_SIZE=2048 +CONFIG_MAIN_TASK_STACK_SIZE=2560 CONFIG_IPC_TASK_STACK_SIZE=1024 CONFIG_CONSOLE_UART_DEFAULT=y # CONFIG_CONSOLE_UART_CUSTOM is not set diff --git a/sdkconfig.old b/sdkconfig.old index 7b2d5b3..cbceaca 100644 --- a/sdkconfig.old +++ b/sdkconfig.old @@ -130,8 +130,8 @@ CONFIG_PARTITION_TABLE_MD5=y # # Audio HAL # -# CONFIG_AUDIO_BOARD_CUSTOM is not set -CONFIG_ESP_LYRAT_V4_3_BOARD=y +CONFIG_AUDIO_BOARD_CUSTOM=y +# CONFIG_ESP_LYRAT_V4_3_BOARD is not set # CONFIG_ESP_LYRAT_V4_2_BOARD is not set # CONFIG_ESP_LYRATD_MSC_V2_1_BOARD is not set # CONFIG_ESP_LYRATD_MSC_V2_2_BOARD is not set @@ -140,10 +140,51 @@ CONFIG_ESP_LYRAT_V4_3_BOARD=y # CONFIG_ESP32_S2_KALUGA_1_V1_2_BOARD is not set # end of Audio HAL +# +# Custom Audio Board +# +# CONFIG_DAC_PCM51XX is not set +# CONFIG_DAC_PCM5102A is not set +# CONFIG_DAC_MA120 is not set +# CONFIG_DAC_MA120X0 is not set +CONFIG_DAC_ADAU1961=y + +# +# DAC I2C control interface +# +CONFIG_DAC_I2C_SDA=12 +CONFIG_DAC_I2C_SCL=14 +CONFIG_DAC_I2C_ADDR=0x70 +# end of DAC I2C control interface + +# +# I2S master interface +# +CONFIG_MASTER_I2S_MCLK_PIN=3 +CONFIG_MASTER_I2S_BCK_PIN=15 +CONFIG_MASTER_I2S_LRCK_PIN=13 +CONFIG_MASTER_I2S_DATAOUT_PIN=4 +# end of I2S master interface + +# +# I2S slave interface +# +CONFIG_SLAVE_I2S_BCK_PIN=26 +CONFIG_SLAVE_I2S_LRCK_PIN=12 +CONFIG_SLAVE_I2S_DATAOUT_PIN=5 +# end of I2S slave interface +# end of Custom Audio Board + # # ESP32 DSP processor config # -# CONFIG_USE_DSP_PROCESSOR is not set +CONFIG_USE_DSP_PROCESSOR=y +# CONFIG_SNAPCLIENT_DSP_FLOW_STEREO is not set +# CONFIG_SNAPCLIENT_DSP_FLOW_BASSBOOST is not set +# CONFIG_SNAPCLIENT_DSP_FLOW_BIAMP is not set +CONFIG_SNAPCLIENT_DSP_FLOW_BASS_TREBLE_EQ=y +CONFIG_USE_BIQUAD_ASM=y +# CONFIG_SNAPCLIENT_USE_SOFT_VOL is not set # end of ESP32 DSP processor config # @@ -153,24 +194,6 @@ CONFIG_SNTP_TIMEZONE="UTC" CONFIG_SNTP_SERVER="pool.ntp.org" # end of SNTP Configuration -# -# Application Configuration -# - -# -# HTTP Server Setting -# -CONFIG_WEB_PORT=8000 -# end of HTTP Server Setting - -# -# GPIO Setting -# -CONFIG_GPIO_RANGE_MAX=33 -CONFIG_BLINK_GPIO=5 -# end of GPIO Setting -# end of Application Configuration - # # Wifi Configuration # @@ -183,6 +206,12 @@ CONFIG_WIFI_MAXIMUM_RETRY=0 # CONFIG_SNAPSERVER_USE_MDNS=y CONFIG_SNAPCLIENT_NAME="esp-snapclient" + +# +# HTTP Server Setting +# +CONFIG_WEB_PORT=8000 +# end of HTTP Server Setting # end of Snapcast Configuration # @@ -407,7 +436,7 @@ CONFIG_ADC_CAL_LUT_ENABLE=y CONFIG_ESP_ERR_TO_NAME_LOOKUP=y CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_ESP_MAIN_TASK_STACK_SIZE=2048 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=2560 CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 @@ -562,7 +591,7 @@ CONFIG_WIFI_LOG_DEFAULT_LEVEL_INFO=y # CONFIG_WIFI_LOG_DEFAULT_LEVEL_DEBUG is not set # CONFIG_WIFI_LOG_DEFAULT_LEVEL_VERBOSE is not set # CONFIG_ESP32_WIFI_IRAM_OPT is not set -# CONFIG_ESP32_WIFI_RX_IRAM_OPT is not set +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set @@ -1284,7 +1313,7 @@ CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y # CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 -CONFIG_MAIN_TASK_STACK_SIZE=2048 +CONFIG_MAIN_TASK_STACK_SIZE=2560 CONFIG_IPC_TASK_STACK_SIZE=1024 CONFIG_CONSOLE_UART_DEFAULT=y # CONFIG_CONSOLE_UART_CUSTOM is not set diff --git a/sdkconfig_lyrat_v4.3 b/sdkconfig_lyrat_v4.3 new file mode 100644 index 0000000..ccb8dee --- /dev/null +++ b/sdkconfig_lyrat_v4.3 @@ -0,0 +1,1378 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET="esp32" +CONFIG_IDF_TARGET_ESP32=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 +# CONFIG_BOOTLOADER_SPI_CUSTOM_WP_PIN is not set +CONFIG_BOOTLOADER_SPI_WP_PIN=7 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y +# CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# end of Security features + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_NO_STUB is not set +CONFIG_ESPTOOLPY_FLASHMODE_QIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +# CONFIG_ESPTOOLPY_FLASHMODE_DIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Audio HAL +# +# CONFIG_AUDIO_BOARD_CUSTOM is not set +CONFIG_ESP_LYRAT_V4_3_BOARD=y +# CONFIG_ESP_LYRAT_V4_2_BOARD is not set +# CONFIG_ESP_LYRATD_MSC_V2_1_BOARD is not set +# CONFIG_ESP_LYRATD_MSC_V2_2_BOARD is not set +# CONFIG_ESP_LYRAT_MINI_V1_1_BOARD is not set +# CONFIG_ESP32_KORVO_DU1906_BOARD is not set +# CONFIG_ESP32_S2_KALUGA_1_V1_2_BOARD is not set +# end of Audio HAL + +# +# ESP32 DSP processor config +# +CONFIG_USE_DSP_PROCESSOR=y +# CONFIG_SNAPCLIENT_DSP_FLOW_STEREO is not set +# CONFIG_SNAPCLIENT_DSP_FLOW_BASSBOOST is not set +# CONFIG_SNAPCLIENT_DSP_FLOW_BIAMP is not set +CONFIG_SNAPCLIENT_DSP_FLOW_BASS_TREBLE_EQ=y +CONFIG_USE_BIQUAD_ASM=y +# CONFIG_SNAPCLIENT_USE_SOFT_VOL is not set +# end of ESP32 DSP processor config + +# +# SNTP Configuration +# +CONFIG_SNTP_TIMEZONE="UTC" +CONFIG_SNTP_SERVER="pool.ntp.org" +# end of SNTP Configuration + +# +# Application Configuration +# + +# +# HTTP Server Setting +# +CONFIG_WEB_PORT=8000 +# end of HTTP Server Setting + +# +# GPIO Setting +# +CONFIG_GPIO_RANGE_MAX=33 +CONFIG_BLINK_GPIO=5 +# end of GPIO Setting +# end of Application Configuration + +# +# Wifi Configuration +# +CONFIG_ENABLE_WIFI_PROVISIONING=y +CONFIG_WIFI_MAXIMUM_RETRY=0 +# end of Wifi Configuration + +# +# Snapcast Configuration +# +CONFIG_SNAPSERVER_USE_MDNS=y +CONFIG_SNAPCLIENT_NAME="esp-snapclient" +# end of Snapcast Configuration + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +CONFIG_COMPILER_OPTIMIZATION_PERF=y +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_TRAX is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 +CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 +CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 +CONFIG_BT_CTRL_MODE_EFF=1 +CONFIG_BT_CTRL_BLE_MAX_ACT=10 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 +CONFIG_BT_CTRL_PINNED_TO_CORE=0 +CONFIG_BT_CTRL_HCI_TL=1 +CONFIG_BT_CTRL_ADV_DUP_FILT_MAX=30 +CONFIG_BT_CTRL_HW_CCA_EFF=0 +CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF=0 +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP=y +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM=100 +CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 +CONFIG_BT_CTRL_BLE_SCAN_DUPL=y +CONFIG_BT_CTRL_SCAN_DUPL_TYPE=0 +CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE=100 +CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF=0 +CONFIG_BT_CTRL_SLEEP_MODE_EFF=0 +CONFIG_BT_CTRL_SLEEP_CLOCK_EFF=0 +CONFIG_BT_CTRL_HCI_TL_EFF=1 +CONFIG_BT_RESERVE_DRAM=0 +CONFIG_BT_NIMBLE_USE_ESP_TIMER=y +# end of Bluetooth + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +# CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set +# end of SPI configuration + +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set +# CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set +# CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set +# CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set +# end of TWAI configuration + +# +# UART configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART configuration + +# +# RTCIO configuration +# +# CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC is not set +# end of RTCIO configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set +# end of GPIO Configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set +CONFIG_EFUSE_MAX_BLK_LEN=192 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ESP32-specific +# +CONFIG_ESP32_REV_MIN_0=y +# CONFIG_ESP32_REV_MIN_1 is not set +# CONFIG_ESP32_REV_MIN_2 is not set +# CONFIG_ESP32_REV_MIN_3 is not set +CONFIG_ESP32_REV_MIN=0 +CONFIG_ESP32_DPORT_WORKAROUND=y +# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set +# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 +# CONFIG_ESP32_SPIRAM_SUPPORT is not set +# CONFIG_ESP32_TRAX is not set +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP32_ULP_COPROC_ENABLED is not set +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_BROWNOUT_DET=y +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0 is not set +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set +CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4=y +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set +CONFIG_ESP32_BROWNOUT_DET_LVL=4 +CONFIG_ESP32_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +# CONFIG_ESP32_XTAL_FREQ_26 is not set +# CONFIG_ESP32_XTAL_FREQ_AUTO is not set +CONFIG_ESP32_XTAL_FREQ=40 +# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set +# CONFIG_ESP32_NO_BLOBS is not set +# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set +# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set +# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set +CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5 +# end of ESP32-specific + +# +# ADC-Calibration +# +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y +# end of ADC-Calibration + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=2048 +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y +CONFIG_ETH_PHY_INTERFACE_RMII=y +# CONFIG_ETH_PHY_INTERFACE_MII is not set +CONFIG_ETH_RMII_CLK_INPUT=y +# CONFIG_ETH_RMII_CLK_OUTPUT is not set +CONFIG_ETH_RMII_CLK_IN_GPIO=0 +CONFIG_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ETH_DMA_RX_BUFFER_NUM=10 +CONFIG_ETH_DMA_TX_BUFFER_NUM=10 +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_USE_OPENETH is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +# CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR is not set +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y +# end of ESP NETIF Adapter + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# end of Power Management + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_PD_FLASH=y + +# +# Memory protection +# +# end of Memory protection +# end of ESP System Settings + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=2048 +# CONFIG_ESP_TIMER_IMPL_FRC2 is not set +CONFIG_ESP_TIMER_IMPL_TG0_LAC=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=8 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=64 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=8 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=8 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=16 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_WIFI_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_VERBOSE is not set +# CONFIG_ESP32_WIFI_IRAM_OPT is not set +# CONFIG_ESP32_WIFI_RX_IRAM_OPT is not set +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# end of Wi-Fi + +# +# PHY +# +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# end of PHY + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_PORT_TASK_PRIO=10 +CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_FMB_TIMER_PORT_ENABLED=y +CONFIG_FMB_TIMER_GROUP=0 +CONFIG_FMB_TIMER_INDEX=0 +# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set +# end of Modbus configuration + +# +# FreeRTOS +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_HZ=1000 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +# CONFIG_FREERTOS_ASSERT_FAIL_ABORT is not set +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +CONFIG_FREERTOS_ASSERT_DISABLE=y +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=768 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=10 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=1536 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=5 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# CONFIG_FREERTOS_FPU_IN_ISR is not set +# end of FreeRTOS + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=6 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +# CONFIG_LWIP_SO_REUSE_RXTOALL is not set +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=6 +CONFIG_LWIP_MAX_LISTENING_TCP=6 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1460 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=11680 +CONFIG_LWIP_TCP_WND_DEFAULT=11680 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=10 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +CONFIG_LWIP_TCP_SACK_OUT=y +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=1 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x0 +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# Certificate Bundle +# +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y +CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +CONFIG_MDNS_TASK_STACK_SIZE=2816 +CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_MDNS_TASK_AFFINITY_CPU0 is not set +# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set +CONFIG_MDNS_TASK_AFFINITY=0x7FFFFFFF +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +# CONFIG_MDNS_STRICT_MODE is not set +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set +# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# end of Websocket +# end of TCP Transport + +# +# TinyUSB +# +# end of TinyUSB + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# end of Supplicant + +# +# DSP Library +# +# CONFIG_DSP_ANSI is not set +CONFIG_DSP_OPTIMIZED=y +CONFIG_DSP_OPTIMIZATION=1 +# CONFIG_DSP_MAX_FFT_SIZE_512 is not set +# CONFIG_DSP_MAX_FFT_SIZE_1024 is not set +# CONFIG_DSP_MAX_FFT_SIZE_2048 is not set +CONFIG_DSP_MAX_FFT_SIZE_4096=y +# CONFIG_DSP_MAX_FFT_SIZE_8192 is not set +# CONFIG_DSP_MAX_FFT_SIZE_16384 is not set +# CONFIG_DSP_MAX_FFT_SIZE_32768 is not set +CONFIG_DSP_MAX_FFT_SIZE=4096 +# end of DSP Library + +# +# WebSocket Server +# +CONFIG_WEBSOCKET_SERVER_MAX_CLIENTS=1 +CONFIG_WEBSOCKET_SERVER_QUEUE_SIZE=2 +CONFIG_WEBSOCKET_SERVER_QUEUE_TIMEOUT=30 +CONFIG_WEBSOCKET_SERVER_TASK_STACK_DEPTH=3000 +CONFIG_WEBSOCKET_SERVER_TASK_PRIORITY=5 +# CONFIG_WEBSOCKET_SERVER_PINNED is not set +# end of WebSocket Server +# end of Component config + +# +# Compatibility options +# +# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set +# end of Compatibility options + +# Deprecated options for backward compatibility +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +CONFIG_APP_ROLLBACK_ENABLE=y +# CONFIG_APP_ANTI_ROLLBACK is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +CONFIG_FLASHMODE_QIO=y +# CONFIG_FLASHMODE_QOUT is not set +# CONFIG_FLASHMODE_DIO is not set +# CONFIG_FLASHMODE_DOUT is not set +# CONFIG_MONITOR_BAUD_9600B is not set +# CONFIG_MONITOR_BAUD_57600B is not set +CONFIG_MONITOR_BAUD_115200B=y +# CONFIG_MONITOR_BAUD_230400B is not set +# CONFIG_MONITOR_BAUD_921600B is not set +# CONFIG_MONITOR_BAUD_2MB is not set +# CONFIG_MONITOR_BAUD_OTHER is not set +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_DISABLE_GCC8_WARNINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_ADC2_DISABLE_DAC=y +# CONFIG_SPIRAM_SUPPORT is not set +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +# CONFIG_ULP_COPROC_ENABLED is not set +CONFIG_ULP_COPROC_RESERVE_MEM=0 +CONFIG_BROWNOUT_DET=y +# CONFIG_BROWNOUT_DET_LVL_SEL_0 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +CONFIG_BROWNOUT_DET_LVL_SEL_4=y +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set +CONFIG_BROWNOUT_DET_LVL=4 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set +# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=2048 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +# CONFIG_POST_EVENTS_FROM_IRAM_ISR is not set +# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set +CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y +# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP32S2_PANIC_GDBSTUB is not set +CONFIG_TIMER_TASK_STACK_SIZE=2048 +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=1536 +CONFIG_TIMER_QUEUE_LENGTH=5 +# CONFIG_L2_TO_L3_COPY is not set +# CONFIG_USE_ONLY_LWIP_SELECT is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1460 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=11680 +CONFIG_TCP_WND_DEFAULT=11680 +CONFIG_TCP_RECVMBOX_SIZE=10 +CONFIG_TCP_QUEUE_OOSEQ=y +# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +# CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_TCPIP_TASK_AFFINITY_CPU0=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x0 +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# End of deprecated options