hexianglong/snapclient
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- add eclipse project configuration

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- use espressif ADF, remove external opus rep
  o uses audio pipelines now
- change code to use flac decoder
- remove mersus code
- add first try of audio synchronization
  o needed to sync timeofday to server on reception of server settings to avoid overflows in timeval calculations (int32_t on esp32 SDK)
  o still a lot of TODO's in the code, but it's almost in sync, although there is quite some chunk skipping which I am currently working on
This commit is contained in:
Carlos
2020-12-13 22:19:40 +01:00
Unverified
parent abcb00b616
commit 1e1893bb49
46 changed files with 1174 additions and 4115 deletions
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17
.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1018780958">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1018780958" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.pathentry">
<pathentry kind="src" path=""/>
<pathentry excluding="**/CMakeFiles/**" kind="out" path="build"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>

3
.gitmodules vendored
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[submodule "components/opus/opus"]
path = components/opus/opus
url = https://github.com/xiph/opus

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.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>snapclient</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.core.cBuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.espressif.idf.core.idfNature</nature>
</natures>
</projectDescription>

5
LICENSE Normal file
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Code in this repository is in the Public Domain (or CC0 licensed, at your option.)
Unless required by applicable law or agreed to in writing, this
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied.

9
Makefile
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#
# This is a project Makefile. It is assumed the directory this Makefile resides in is a
# project subdirectory.
#
PROJECT_NAME := snapclient
include $(IDF_PATH)/make/project.mk

2
components/MerusAudio/CMakeLists.txt
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idf_component_register(SRCS "MerusAudio.c"
INCLUDE_DIRS "include")

52
components/MerusAudio/Kconfig.projbuild
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menu "Merus MA120x0 interface Configuration"
config MA120X0_NENABLE_PIN
int "Master enable/disable for ma120x0"
default 16
help
GPIO number to control enable/disable.
config MA120X0_NMUTE_PIN
int "Master mute/unmute for ma120x0"
default 2
help
GPIO number to controm mute/unmute.
config MA120X0_ENABLE_PIN
int "Master enable/disable for ma120x0"
default 16
help
GPIO number to control enable/disable.
config MA120X0_NERR_PIN
int "NERR monitor pin"
default 21
help
GPIO number to monitor NERROR.
config MA120X0_NCLIP_PIN
int "Clip indication pin"
default 22
help
GPIO number low if clip observed
config MA120X0_SCL_PIN
int "I2C_SCL clock GPIO"
default 0
help
GPIO number to use for I2C clock.
config MA120X0_SDA_PIN
int "I2C_SDA data GPIO"
default 4
help
GPIO number to use for I2C data.
config MA120X0_I2C_ADDR
hex "I2C ADDR"
default 0x20
help
Address for ma120x0.
endmenu

432
components/MerusAudio/MerusAudio.c
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//
// MA120x0P ESP32 Driver
//
// Merus Audio - September 2018
// Written by Joergen Kragh Jakobsen, jkj@myrun.dk
//
// Register interface thrugh I2C for MA12070P and MA12040P
// Support a single amplifier/i2c address
//
//
#include <stdio.h>
#include <stdint.h>
#include "esp_log.h"
#include "driver/i2c.h"
#include "MerusAudio.h"
#include "ma120x0.h"
//#include "ma120_rev1_all.h"
#define MA_NENABLE_IO CONFIG_MA120X0_NENABLE_PIN
#define MA_ENABLE_IO CONFIG_MA120X0_ENABLE_PIN
#define MA_NMUTE_IO CONFIG_MA120X0_NMUTE_PIN
#define MA_NERR_IO CONFIG_MA120X0_NERR_PIN
#define MA_NCLIP_IO CONFIG_MA120X0_NCLIP_PIN
static const char* I2C_TAG = "i2c";
#define I2C_CHECK(a, str, ret) if(!(a)) { \
ESP_LOGE(I2C_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
return (ret); \
}
#define I2C_MASTER_SCL_IO CONFIG_MA120X0_SCL_PIN //4 /*!< gpio number for I2C master clock */
#define I2C_MASTER_SDA_IO CONFIG_MA120X0_SDA_PIN //0
/*!< gpio number for I2C master data */
#define I2C_MASTER_NUM I2C_NUM_0
/*!< I2C port number for master dev */
#define I2C_MASTER_TX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_FREQ_HZ 100000 /*!< I2C master clock frequency */
#define MA120X0_ADDR CONFIG_MA120X0_I2C_ADDR /*!< slave address for MA120X0 amplifier */
#define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
#define READ_BIT I2C_MASTER_READ /*!< I2C master read */
#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
#define ACK_VAL 0x0 /*!< I2C ack value */
#define NACK_VAL 0x1 /*!< I2C nack value */
void setup_ma120x0()
{ // Setup control pins nEnable and nMute
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL<<MA_NENABLE_IO | 1ULL<<MA_NMUTE_IO);
io_conf.pull_down_en = 0;
io_conf.pull_up_en = 0;
gpio_config(&io_conf);
gpio_set_level(MA_NMUTE_IO, 0);
gpio_set_level(MA_NENABLE_IO, 1);
i2c_master_init();
gpio_set_level(MA_NENABLE_IO, 0);
uint8_t res = ma_read_byte(MA120X0_ADDR,1,MA_hw_version__a);
printf("Hardware version: 0x%02x\n",res);
ma_write_byte(MA120X0_ADDR,1,MA_i2s_format__a,8); // Set i2s left justified, set audio_proc_enable
ma_write_byte(MA120X0_ADDR,1,MA_vol_db_master__a,0x50); // Set vol_db_master
res = ma_read_byte(MA120X0_ADDR,1,MA_error__a);
printf("Errors : 0x%02x\n",res);
res = 01; // get_MA_audio_in_mode_mon();
printf("Audio in mode : 0x%02x\n",res);
printf("Clear errors\n");
ma_write_byte(MA120X0_ADDR,1,45,0x34);
ma_write_byte(MA120X0_ADDR,1,45,0x30);
printf("MA120x0P init done\n");
gpio_set_level(MA_NMUTE_IO, 1);
printf("Unmute\n");
}
void setup_ma120()
{
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL<<MA_ENABLE_IO | 1ULL<<MA_NMUTE_IO );
io_conf.pull_down_en = 0;
io_conf.pull_up_en = 0;
printf("setup output %d %d \n",MA_ENABLE_IO, MA_NMUTE_IO);
gpio_config(&io_conf);
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.mode = GPIO_MODE_INPUT;
io_conf.pin_bit_mask = (1ULL<<MA_NCLIP_IO | 1ULL<<MA_NERR_IO );
io_conf.pull_down_en = 0;
io_conf.pull_up_en = 0;
printf("setup input %d %d \n",MA_NCLIP_IO, MA_NERR_IO);
gpio_config(&io_conf);
gpio_set_level(MA_NMUTE_IO, 0);
gpio_set_level(MA_ENABLE_IO, 0);
i2c_master_init();
gpio_set_level(MA_ENABLE_IO, 1);
uint8_t res = ma_write_byte(0x20,2,1544,0);
res = ma_read_byte(0x20,2,1544);
printf("Hardware version: 0x%02x\n",res);
printf("Scan I2C bus: ");
for (uint8_t addr = 0x20; addr <= 0x23 ; addr++ )
{ res = ma_read_byte(addr,2,0);
printf(" 0x%02x => GEN2 ,",addr);
//printf("Scan i2c address 0x%02x read address 0 : 0x%02x \n", addr ,res);
}
printf("\n");
uint8_t rxbuf[32];
uint8_t otp[1024];
for (uint8_t i=0;i<16; i++)
{ ma_read(0x20,2,0x8000+i*32,rxbuf,32);
//printf("%04x : ",0x8000+i*32 );
for (uint8_t j=0; j<32 ; j++ )
{ otp[i*32+j] = rxbuf[j];
}
}
for (uint16_t i=0;i<16*32; i++)
{ if (i%32==0) {
printf("\n0x%04x : ",0x8000+i);
}
printf("%02x ",otp[i]);
}
res = ma_write_byte(0x20,2,0x060c,0);
res = ma_read_byte(0x20,2,0x060c);
printf("\nHardware version: 0x%02x\n",res);
printf("\n");
}
uint8_t b[32];
#define CHECK(ADDR,L) ma_read(0x20,2,ADDR,b,L); printf("Check 0x%04x :",ADDR); for (int ci=0;ci<L;ci++) printf(" 0x%02x",b[ci]); printf("\n");
void ma120_setup_audio(uint8_t i2c_addr)
{ uint8_t cmd[32];
//system("$SCOM w 0x0003 0x50 0x50 0x02");
cmd[0] = 0x50;
cmd[1] = 0x50;
cmd[2] = 0x02;
ma_write(i2c_addr,2,0x0003,cmd,3);
//CHECK(0x0003,3);
//system("$SCOM w 0x0015 0x12");
ma_write_byte(i2c_addr,2,0x0015, 0x12);
//CHECK(0x0015,1);
//system("$SCOM w 0x0025 0x0e");
ma_write_byte(i2c_addr,2,0x0025, 0x0e);
//CHECK(0x0025,1);
//system("$SCOM w 0x003d 0x73");
//system("$SCOM w 0x003d 0xfe 0x03");
cmd[0] = 0xfe;
cmd[1] = 0x03;
ma_write(i2c_addr,2,0x003d,cmd,2);
//CHECK(0x003d,2);
//system("$SCOM w 0x0040 0xf0 0x03");
cmd[0] = 0xf0;
cmd[1] = 0x03;
ma_write(i2c_addr,2,0x0040,cmd,2);
//CHECK(0x0040,2);
//system("$SCOM w 0x0043 0xf0 0x07");
cmd[0] = 0xf0;
cmd[1] = 0x07;
ma_write(i2c_addr,2,0x0043,cmd,2);
//CHECK(0x0043,2);
//system("$SCOM w 0x0079 0x9b");
ma_write_byte(i2c_addr,2,0x0079, 0x9b);
//CHECK(0x0079,1);
//system("$SCOM w 0x008e 0xef");
ma_write_byte(i2c_addr,2,0x008e, 0xef);
//CHECK(0x008e,1);
//system("$SCOM w 0x0090 0x20 0x32 0x45");
cmd[0] = 0x20;
cmd[1] = 0x32;
cmd[2] = 0x45;
ma_write(i2c_addr,2,0x0090,cmd,3);
//CHECK(0x0090,3);
//system("$SCOM w 0x00c0 0x7c");
ma_write_byte(i2c_addr,2,0x00c0, 0x7c);
//CHECK(0x00c0,1);
//system("$SCOM w 0x00c3 0x07 0xff");
cmd[0] = 0x07;
cmd[1] = 0xff;
ma_write(i2c_addr,2,0x00c3,cmd,2);
//CHECK(0x00c3,2);
//system("$SCOM w 0x00d9 0xd6");
ma_write_byte(i2c_addr,2,0x00d9, 0xd6);
//CHECK(0x00d9,1);
//------------- not imp
//system("$SCOM w 0x00f0 0x00 0x00");
cmd[0] = 0x00;
cmd[1] = 0x00;
ma_write(i2c_addr,2,0x00f0,cmd,2);
//CHECK(0x00f0,2);
//system("$SCOM w 0x010f 0x0f 0x0f 0x64");
cmd[0] = 0x0f;
cmd[1] = 0x0f;
cmd[2] = 0x64;
ma_write(i2c_addr,2,0x010f,cmd,3);
//CHECK(0x010f,3);
//system("$SCOM w 0x0140 0x5c");
ma_write_byte(i2c_addr,2,0x0140, 0x5c);
//CHECK(0x0140,1);
//system("$SCOM w 0x0152 0x00 0x77 0x00");
cmd[0] = 0x00;
cmd[1] = 0x77;
cmd[2] = 0x00;
ma_write(i2c_addr,2,0x0152,cmd,3);
//CHECK(0x0152,3);
//system("$SCOM w 0x025d 0x0a");
ma_write_byte(i2c_addr,2,0x025d, 0x0a);
//CHECK(0x025d,1);
//system("$SCOM w 0x025f 0x4d");
ma_write_byte(i2c_addr,2,0x025f, 0x4d);
//CHECK(0x025f,1);
//system("$SCOM w 0x050b 0x3f");
ma_write_byte(i2c_addr,2,0x050b, 0x3f);
//CHECK(0x050b,1);
const char dsp0[16] = {0x10 ,0x00 ,0x40 ,0x00 ,0x13 ,0xb6 ,0x40 ,0x00 ,0x13 ,0x47 ,0x41 ,0x00 ,0x15 ,0x06 ,0x00 ,0x00};
const char dsp1[16] = {0x15 ,0x17 ,0x00 ,0x00 ,0x15 ,0x47 ,0x40 ,0x00 ,0x13 ,0x56 ,0x41 ,0x00 ,0x13 ,0x67 ,0x41 ,0x00};
const char dsp2[16] = {0x15 ,0x26 ,0x00 ,0x00 ,0x15 ,0x37 ,0x00 ,0x00 ,0x13 ,0x76 ,0x41 ,0x00 ,0x13 ,0x87 ,0x41 ,0x00};
const char dsp3[16] = {0x15 ,0x46 ,0x00 ,0x00 ,0x15 ,0x57 ,0x00 ,0x00 ,0x10 ,0x30 ,0x40 ,0x00};
ma_write(i2c_addr,2,0x1000,dsp0,16);
ma_write(i2c_addr,2,0x1010,dsp1,16);
ma_write(i2c_addr,2,0x1020,dsp2,16);
ma_write(i2c_addr,2,0x1030,dsp3,12);
//CHECK(0x1000,16);
//CHECK(0x1010,16);
//CHECK(0x1020,16);
//CHECK(0x1030,16);
//system("$SCOM w 0x1000 0x10 0x00 0x40 0x00 0x13 0xb6 0x40 0x00 0x13 0x47 0x41 0x00 0x15 0x06 0x00 0x00");
//system("$SCOM w 0x1010 0x15 0x17 0x00 0x00 0x15 0x47 0x40 0x00 0x13 0x56 0x41 0x00 0x13 0x67 0x41 0x00");
//system("$SCOM w 0x1020 0x15 0x26 0x00 0x00 0x15 0x37 0x00 0x00 0x13 0x76 0x41 0x00 0x13 0x87 0x41 0x00");
//system("$SCOM w 0x1030 0x15 0x46 0x00 0x00 0x15 0x57 0x00 0x00 0x10 0x30 0x40 0x00");
printf("Audio setup done\n");
ma_write_byte(0x20,2,0x608,0x33);
ma_write_byte(0x20,2,0x609,0);
// ma_write_byte(0x20,2,513,0x11);
//ma_write_byte(i2c_addr,2,MA_core__test__d1_mux_sel__a, 0x03);
gpio_set_level(MA_NMUTE_IO, 0);
}
//var sys_err1_str = ['X','X','DSP3','DSP2','DSP1','DSP0','ERR','PVT_low'];
//var sys_err0_str = ['TW','AUD','CLK','PV_ov','PV_low','PV_uv','OTE','OTW'];
//const char * syserr1_str = { "X", "X", "DSP3","DSP2","DSP1","DSP0","ERR","PVT_low" } ;
//const char * syserr0_str = { "TW","AUD","CLK","PV_ov","PV_low","PV_uv","OTE","OTW" } ;
void ma120_read_error(uint8_t i2c_addr)
{ //0x0118 error now ch0 [clip_stuck dc vcf_err ocp_severe ocp]
//0x0119 error now ch1 [clip_stuck dc vcf_err ocp_severe ocp]
//0x011a error now system [ AE CE ... ]
//0x011b error now system [DSP3 DSP2 DSP1 DSP0 OC OE]
//0x011c error acc ch0 [clip_stuck dc vcf_err ocp_severe ocp]
//0x011d error acc ch1 [clip_stuck dc vcf_err ocp_severe ocp]
//0x011e error acc system [7..0]
//0x011f error acc system [13..8]
uint8_t rxbuf[10] = {0};
char * l1;
l1 = malloc(40);
uint8_t res = 0xff ; // ma_read(i2c_addr,2,MA_core__prot_sys__errVect_now__errVector_ch0__a,rxbuf,8);
//for (int i = 0; i<=7;i++)
//{
// printf("%d %s",i,((rxbuf[2] & (1<<i))==(1<<i)) ? sysstr0_str[i] : " ");
//}
//printf("0x011b : 0x%02x %s", rxbuf[2], l1 );
printf("\nError vectors :");
for (int i = 0; i<8; i++)
{ printf("%02x ", rxbuf[i]);
}
printf("\n");
}
void i2c_master_init()
{ int i2c_master_port = I2C_MASTER_NUM;
i2c_config_t conf;
conf.mode = I2C_MODE_MASTER;
conf.sda_io_num = I2C_MASTER_SDA_IO;
conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
conf.scl_io_num = I2C_MASTER_SCL_IO;
conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
conf.master.clk_speed = I2C_MASTER_FREQ_HZ;
esp_err_t res = i2c_param_config(i2c_master_port, &conf);
printf("Driver param setup : %d\n",res);
res = i2c_driver_install(i2c_master_port, conf.mode, I2C_MASTER_RX_BUF_DISABLE, I2C_MASTER_TX_BUF_DISABLE, 0);
printf("Driver installed : %d\n",res);
}
esp_err_t ma_write( uint8_t i2c_addr,uint8_t prot, uint16_t address, uint8_t *wbuf, uint8_t n)
{
bool ack = ACK_VAL;
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, i2c_addr<<1 | WRITE_BIT, ACK_CHECK_EN);
if (prot == 2) {
i2c_master_write_byte(cmd, (uint8_t)((address&0xff00)>>8), ACK_VAL);
i2c_master_write_byte(cmd, (uint8_t)(address&0x00ff), ACK_VAL);
} else
{
i2c_master_write_byte(cmd, (uint8_t) address, ACK_VAL);
}
for (int i=0 ; i<n ; i++)
{ if (i==n-1) ack = NACK_VAL;
i2c_master_write_byte(cmd, wbuf[i], ack);
}
i2c_master_stop(cmd);
int ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
if (ret == ESP_FAIL) { return ret; }
return ESP_OK;
}
esp_err_t ma_write_byte(uint8_t i2c_addr,uint8_t prot, uint16_t address, uint8_t value)
{ printf("%04x %02x\n",address,value);
esp_err_t ret=0;
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, (i2c_addr<<1) | WRITE_BIT , ACK_CHECK_EN);
if (prot == 2) {
i2c_master_write_byte(cmd, (uint8_t)((address&0xff00)>>8), ACK_VAL);
i2c_master_write_byte(cmd, (uint8_t)(address&0x00ff), ACK_VAL);
} else
{
i2c_master_write_byte(cmd, (uint8_t) address, ACK_VAL);
}
i2c_master_write_byte(cmd, value, ACK_VAL);
i2c_master_stop(cmd);
ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
if (ret == ESP_FAIL) {
printf("ESP_I2C_WRITE ERROR : %d\n",ret);
return ret;
}
return ESP_OK;
}
esp_err_t ma_read(uint8_t i2c_addr, uint8_t prot, uint16_t address, uint8_t *rbuf, uint8_t n)
{ esp_err_t ret;
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
if (cmd == NULL ) { printf("ERROR handle null\n"); }
i2c_master_start(cmd);
i2c_master_write_byte(cmd, (i2c_addr<<1) | WRITE_BIT, ACK_CHECK_EN);
if (prot == 2) {
i2c_master_write_byte(cmd, (uint8_t)((address&0xff00)>>8), ACK_VAL);
i2c_master_write_byte(cmd, (uint8_t)(address&0x00ff), ACK_VAL);
} else
{
i2c_master_write_byte(cmd, (uint8_t) address, ACK_VAL);
}
i2c_master_start(cmd);
i2c_master_write_byte(cmd, (i2c_addr<<1) | READ_BIT, ACK_CHECK_EN);
i2c_master_read(cmd, rbuf, n-1 ,ACK_VAL);
// for (uint8_t i = 0;i<n;i++)
// { i2c_master_read_byte(cmd, rbuf++, ACK_VAL); }
i2c_master_read_byte(cmd, rbuf + n-1 , NACK_VAL);
i2c_master_stop(cmd);
ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 100 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
if (ret == ESP_FAIL) {
printf("i2c Error read - readback\n");
return ESP_FAIL;
}
return ret;
}
uint8_t ma_read_byte(uint8_t i2c_addr,uint8_t prot, uint16_t address)
{
uint8_t value = 0;
esp_err_t ret;
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd); // Send i2c start on bus
i2c_master_write_byte(cmd, (i2c_addr<<1) | WRITE_BIT, ACK_CHECK_EN );
if (prot == 2) {
i2c_master_write_byte(cmd, (uint8_t)((address&0xff00)>>8), ACK_VAL);
i2c_master_write_byte(cmd, (uint8_t)(address&0x00ff), ACK_VAL);
} else
{
i2c_master_write_byte(cmd, (uint8_t) address, ACK_VAL);
}
i2c_master_start(cmd); // Repeated start
i2c_master_write_byte(cmd, (i2c_addr<<1) | READ_BIT, ACK_CHECK_EN);
i2c_master_read_byte(cmd, &value, NACK_VAL);
i2c_master_stop(cmd);
ret = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
if (ret == ESP_FAIL) {
printf("i2c Error read - readback\n");
return ESP_FAIL;
}
return value;
}

12
components/MerusAudio/component.mk
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@@ -1,12 +0,0 @@
#
# Main Makefile. This is basically the same as a component makefile.
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component_common.mk. By default,
# this will take the sources in the src/ directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the ESP-IDF documents if you need to do this.
#
COMPONENT_SRCDIRS := .
# CFLAGS +=

20
components/MerusAudio/include/MerusAudio.h
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@@ -1,20 +0,0 @@
#ifndef _MERUSAUDIO_H_
#define _MERUSAUDIO_H_
void setup_ma120x0(void);
void setup_ma120(void);
void ma120_read_error(uint8_t i2c_addr);
void ma120_setup_audio(uint8_t i2c_addr);
void i2c_master_init(void);
esp_err_t ma_write_byte(uint8_t i2c_addr, uint8_t prot, uint16_t address, uint8_t value);
esp_err_t ma_write(uint8_t i2c_addr, uint8_t prot, uint16_t address, uint8_t *wbuf, uint8_t n);
uint8_t ma_read_byte(uint8_t i2c_addr, uint8_t prot, uint16_t address);
esp_err_t ma_read(uint8_t i2c_addr, uint8_t prot, uint16_t address, uint8_t *rbuf, uint8_t n);
#endif /* _MERUSAUDIO_H_ */

1226
components/MerusAudio/include/ma120x0.h
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File diff suppressed because it is too large Load Diff

4
components/dsp_processor/CMakeLists.txt
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@@ -1,4 +0,0 @@
idf_component_register(SRCS "dsp_processor.c"
INCLUDE_DIRS "include"
REQUIRES esp-dsp)

53
components/dsp_processor/Kconfig.projbuild
View File

@@ -1,53 +0,0 @@
# Config file for ESP32 DSP Processor
menu "ESP32 audio buffer and I2S pin config"
config USE_PSRAM
bool "Use PSRAM"
default true
help
Need wrover class modules with large SPRAM to have required buffers for Snapcast network delay
config BITS_PER_SAMPLE
int "bits per sample output to i2s driver"
default 32
help
Select number of bits per sample for codec configed and connected to esp32 i2s dma hw
config MASTER_I2S_BCK_PIN
int "Master i2s bck"
default 23
help
Master audio interface bit clock.
config MASTER_I2S_LRCK_PIN
int "Master i2s lrck"
default 13
help
Master audio interface left/right sync clock.
config MASTER_I2S_DATAOUT_PIN
int "Master i2s data out"
default 14
help
Master audio interface data out.
config SLAVE_I2S_BCK_PIN
int "Slave i2s bck"
default 26
help
Slave audio interface bit clock.
config SLAVE_I2S_LRCK_PIN
int "Slave i2s lrck"
default 12
help
Slave audio interface left/right sync clock.
config SLAVE_I2S_DATAOUT_PIN
int "Slave i2s data out"
default 5
help
Slave audio interface data out.
endmenu

11
components/dsp_processor/component.mk
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@@ -1,11 +0,0 @@
#
# Main Makefile. This is basically the same as a component makefile.
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component_common.mk. By default,
# this will take the sources in the src/ directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the ESP-IDF documents if you need to do this.
#
COMPONENT_SRCDIRS := .
# CFLAGS +=

398
components/dsp_processor/dsp_processor.c
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@@ -1,398 +0,0 @@
#include <stdint.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_log.h"
#include "driver/i2s.h"
#include "freertos/ringbuf.h"
#include "dsps_biquad_gen.h"
#include "dsps_biquad.h"
//#include "websocket_if.h"
#include "dsp_processor.h"
uint32_t bits_per_sample = CONFIG_BITS_PER_SAMPLE;
static xTaskHandle s_dsp_i2s_task_handle = NULL;
static RingbufHandle_t s_ringbuf_i2s = NULL;
extern xQueueHandle i2s_queue;
extern uint32_t buffer_ms;
extern uint8_t muteCH[4];
uint dspFlow = dspfStereo;
ptype_t bq[6];
void setup_dsp_i2s(uint32_t sample_rate, bool slave_i2s)
{
i2s_config_t i2s_config0 = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX, // Only TX
.sample_rate = sample_rate,
.bits_per_sample = bits_per_sample,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, // 2-channels
.communication_format = I2S_COMM_FORMAT_I2S ,
.dma_buf_count = 8,
.dma_buf_len = 480,
.intr_alloc_flags = 1, //Default interrupt priority
.use_apll = true,
.fixed_mclk = 0,
.tx_desc_auto_clear = true // Auto clear tx descriptor on underflow
};
i2s_pin_config_t pin_config0 = {
.bck_io_num = CONFIG_MASTER_I2S_BCK_PIN,
.ws_io_num = CONFIG_MASTER_I2S_LRCK_PIN,
.data_out_num = CONFIG_MASTER_I2S_DATAOUT_PIN,
.data_in_num = -1 //Not used
};
i2s_driver_install(0, &i2s_config0, 7, &i2s_queue);
i2s_zero_dma_buffer(0);
i2s_set_pin(0, &pin_config0);
i2s_config_t i2s_config1 = {
.mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only TX - Slave channel
.sample_rate = sample_rate,
.bits_per_sample = bits_per_sample,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, // 2-channels
.communication_format = I2S_COMM_FORMAT_I2S,
.dma_buf_count = 8,
.dma_buf_len = 480,
.use_apll = true,
.fixed_mclk = 0,
.tx_desc_auto_clear = true // Auto clear tx descriptor on underflow
};
i2s_pin_config_t pin_config1 = {
.bck_io_num = CONFIG_SLAVE_I2S_BCK_PIN,
.ws_io_num = CONFIG_SLAVE_I2S_LRCK_PIN,
.data_out_num = CONFIG_SLAVE_I2S_DATAOUT_PIN,
.data_in_num = -1 //Not used
};
if (slave_i2s) {
i2s_driver_install(1, &i2s_config1, 7, &i2s_queue);
i2s_zero_dma_buffer(1);
i2s_set_pin(1, &pin_config1);
}
}
static void dsp_i2s_task_handler(void *arg)
{ uint32_t cnt = 0;
uint8_t *audio = NULL;
float sbuffer0[1024];
float sbuffer1[1024];
float sbuffer2[1024];
float sbufout0[1024];
float sbufout1[1024];
float sbufout2[1024];
float sbuftmp0[1024];
uint8_t dsp_audio[4*1024];
uint8_t dsp_audio1[4*1024];
size_t chunk_size = 0;
size_t bytes_written = 0;
muteCH[0] = 0;
muteCH[1] = 0;
muteCH[2] = 0;
muteCH[3] = 0;
uint32_t inBuffer,freeBuffer,wbuf,rbuf ;
static int32_t avgcnt = 0;
uint32_t avgcntlen = 64; // x 960/4*1/fs = 320ms @48000 kHz
uint32_t avgarray[128] = {0};
uint32_t sum;
float avg ;
for (;;) {
// Condition state Action
// Buffer is empty - because not being filled Stopped Wait
// Buffer is increasing and below target Filling Wait
// Buffer above target Playing Consume from buffer
// Buffer is below target Playing Short delay
cnt++;
audio = (uint8_t *)xRingbufferReceiveUpTo(s_ringbuf_i2s, &chunk_size,(portTickType) 20 ,960); // 200 ms timeout
vRingbufferGetInfo(s_ringbuf_i2s, &freeBuffer, &rbuf, &wbuf, NULL, &inBuffer );
if (avgcnt >= avgcntlen) { avgcnt = 0; }
avgarray[avgcnt++] = inBuffer;
sum = 0;
for (int n = 0; n < avgcntlen ; n++)
{ sum = sum + avgarray[n];
}
avg = sum / avgcntlen;
#ifndef CONFIG_USE_PSRAM
buffer_ms = 150;
#endif
if (inBuffer < (buffer_ms*48*4)) {vTaskDelay(1); }
//audio = (uint8_t *)xRingbufferReceiveUpTo(s_ringbuf_i2s, &chunk_size,(portTickType) 20 ,960); // 200 ms timeout
//audio = (uint8_t *)xRingbufferReceive(s_ringbuf_i2s, &chunk_size, (portTickType)portMAX_DELAY);
if (chunk_size == 0)
{ printf("wait ... buffer : %d\n",inBuffer);
}
//else if (inBuffer < (buffer_ms*48*4))
//{ printf("Buffering ... buffer : %d\n",inBuffer);
//}
else
{ int16_t len = chunk_size/4;
if (cnt%200 < 16)
{ ESP_LOGI("I2S", "Chunk :%d %d %.0f",chunk_size, inBuffer, avg );
//xRingbufferPrintInfo(s_ringbuf_i2s);
}
/*for (uint16_t i=0;i<len;i++)
{
sbuffer0[i] = ((float) ((int16_t) (audio[i*4+1]<<8) + audio[i*4+0]))/32768;
sbuffer1[i] = ((float) ((int16_t) (audio[i*4+3]<<8) + audio[i*4+2]))/32768;
sbuffer2[i] = ((sbuffer0[i]/2) + (sbuffer1[i]/2));
}
*/
switch (dspFlow) {
case dspfStereo :
{ // if (cnt%100==0)
// { ESP_LOGI("I2S", "In dspf Stero :%d",chunk_size);
//ws_server_send_bin_client(0,(char*)audio, 240);
//printf("%d %d \n",byteWritten, i2s_evt.size );
// }
for (uint16_t i=0; i<len; i++)
{ audio[i*4+0] = (muteCH[0] == 1)? 0 : audio[i*4+0];
audio[i*4+1] = (muteCH[0] == 1)? 0 : audio[i*4+1];
audio[i*4+2] = (muteCH[1] == 1)? 0 : audio[i*4+2];
audio[i*4+3] = (muteCH[1] == 1)? 0 : audio[i*4+3];
}
if (bits_per_sample == 16) {
i2s_write(0,(char*)audio, chunk_size, &bytes_written, portMAX_DELAY);
} else
{ i2s_write_expand(0, (char*)audio, chunk_size,16,32, &bytes_written, portMAX_DELAY);
}
}
break;
case dspfBiamp :
{ // Process audio ch0 LOW PASS FILTER
dsps_biquad_f32_ae32(sbuffer0, sbuftmp0, len, bq[0].coeffs, bq[0].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout0, len, bq[1].coeffs, bq[1].w);
// Process audio ch1 HIGH PASS FILTER
dsps_biquad_f32_ae32(sbuffer0, sbuftmp0, len, bq[2].coeffs, bq[2].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout1, len, bq[3].coeffs, bq[3].w);
int16_t valint[2];
for (uint16_t i=0; i<len; i++)
{ valint[0] = (muteCH[0] == 1) ? (int16_t) 0 : (int16_t) (sbufout0[i]*32768);
valint[1] = (muteCH[1] == 1) ? (int16_t) 0 : (int16_t) (sbufout1[i]*32768);
dsp_audio[i*4+0] = (valint[0] & 0xff);
dsp_audio[i*4+1] = ((valint[0] & 0xff00)>>8);
dsp_audio[i*4+2] = (valint[1] & 0xff);
dsp_audio[i*4+3] = ((valint[1] & 0xff00)>>8);
}
if (bits_per_sample == 16) {
i2s_write(0,(char*)audio, chunk_size, &bytes_written, portMAX_DELAY);
} else
{ i2s_write_expand(0, (char*)audio, chunk_size,16,32, &bytes_written, portMAX_DELAY);
}
}
break;
case dspf2DOT1 :
{ // Process audio L + R LOW PASS FILTER
dsps_biquad_f32_ae32(sbuffer2, sbuftmp0, len, bq[0].coeffs, bq[0].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout2, len, bq[1].coeffs, bq[1].w);
// Process audio L HIGH PASS FILTER
dsps_biquad_f32_ae32(sbuffer0, sbuftmp0, len, bq[2].coeffs, bq[2].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout0, len, bq[3].coeffs, bq[3].w);
// Process audio R HIGH PASS FILTER
dsps_biquad_f32_ae32(sbuffer1, sbuftmp0, len, bq[4].coeffs, bq[4].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout1, len, bq[5].coeffs, bq[5].w);
int16_t valint[5];
for (uint16_t i=0; i<len; i++)
{ valint[0] = (muteCH[0] == 1) ? (int16_t) 0 : (int16_t) (sbufout0[i]*32768);
valint[1] = (muteCH[1] == 1) ? (int16_t) 0 : (int16_t) (sbufout1[i]*32768);
valint[2] = (muteCH[2] == 1) ? (int16_t) 0 : (int16_t) (sbufout2[i]*32768);
dsp_audio[i*4+0] = (valint[2] & 0xff);
dsp_audio[i*4+1] = ((valint[2] & 0xff00)>>8);
dsp_audio[i*4+2] = 0;
dsp_audio[i*4+3] = 0;
dsp_audio1[i*4+0] = (valint[0] & 0xff);
dsp_audio1[i*4+1] = ((valint[0] & 0xff00)>>8);
dsp_audio1[i*4+2] = (valint[1] & 0xff);
dsp_audio1[i*4+3] = ((valint[1] & 0xff00)>>8);
}
i2s_write_expand(0, (char*)dsp_audio, chunk_size,16,32, &bytes_written, portMAX_DELAY);
i2s_write_expand(1, (char*)dsp_audio1, chunk_size,16,32, &bytes_written, portMAX_DELAY);
}
break;
case dspfFunkyHonda :
{ // Process audio L + R LOW PASS FILTER
dsps_biquad_f32_ae32(sbuffer2, sbuftmp0, len, bq[0].coeffs, bq[0].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout2, len, bq[1].coeffs, bq[1].w);
// Process audio L HIGH PASS FILTER
dsps_biquad_f32_ae32(sbuffer0, sbuftmp0, len, bq[2].coeffs, bq[2].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout0, len, bq[3].coeffs, bq[3].w);
// Process audio R HIGH PASS FILTER
dsps_biquad_f32_ae32(sbuffer1, sbuftmp0, len, bq[4].coeffs, bq[4].w);
dsps_biquad_f32_ae32(sbuftmp0, sbufout1, len, bq[5].coeffs, bq[5].w);
uint16_t scale = 16384; //32768
int16_t valint[5];
for (uint16_t i=0; i<len; i++)
{ valint[0] = (muteCH[0] == 1) ? (int16_t) 0 : (int16_t) (sbufout0[i]*scale);
valint[1] = (muteCH[1] == 1) ? (int16_t) 0 : (int16_t) (sbufout1[i]*scale);
valint[2] = (muteCH[2] == 1) ? (int16_t) 0 : (int16_t) (sbufout2[i]*scale);
valint[3] = valint[0] + valint[2];
valint[4] = -valint[2] ;
valint[5] = -valint[1] - valint[2] ;
dsp_audio[i*4+0] = (valint[3] & 0xff);
dsp_audio[i*4+1] = ((valint[3] & 0xff00)>>8);
dsp_audio[i*4+2] = (valint[2] & 0xff);
dsp_audio[i*4+3] = ((valint[2] & 0xff00)>>8);
dsp_audio1[i*4+0] = (valint[4] & 0xff);
dsp_audio1[i*4+1] = ((valint[4] & 0xff00)>>8);
dsp_audio1[i*4+2] = (valint[5] & 0xff);
dsp_audio1[i*4+3] = ((valint[5] & 0xff00)>>8);
}
i2s_write_expand(0, (char*)dsp_audio, chunk_size,16,32, &bytes_written, portMAX_DELAY);
i2s_write_expand(1, (char*)dsp_audio1, chunk_size,16,32, &bytes_written, portMAX_DELAY);
}
break;
default :
break;
}
if (cnt%100==0)
{ //ws_server_send_bin_client(0,(char*)audio, 240);
//printf("%d %d \n",byteWritten, i2s_evt.size );
}
vRingbufferReturnItem(s_ringbuf_i2s,(void *)audio);
}
}
}
// buffer size must hold 400ms-1000ms // for 2ch16b48000 that is 76800 - 192000 or 75-188 x 1024
#define BUFFER_SIZE 192*1024
void dsp_i2s_task_init(uint32_t sample_rate,bool slave)
{ setup_dsp_i2s(sample_rate,slave);
#ifdef CONFIG_USE_PSRAM
printf("Setup ringbuffer using PSRAM \n");
StaticRingbuffer_t *buffer_struct = (StaticRingbuffer_t *)heap_caps_malloc(sizeof(StaticRingbuffer_t), MALLOC_CAP_SPIRAM);
printf("Buffer_struct ok\n");
uint8_t *buffer_storage = (uint8_t *)heap_caps_malloc(sizeof(uint8_t)*BUFFER_SIZE, MALLOC_CAP_SPIRAM);
printf("Buffer_stoarge ok\n");
s_ringbuf_i2s = xRingbufferCreateStatic(BUFFER_SIZE, RINGBUF_TYPE_BYTEBUF, buffer_storage, buffer_struct);
printf("Ringbuf ok\n");
#else
printf("Setup ringbuffer using internal ram - only space for 150ms - Snapcast buffer_ms parameter ignored \n");
s_ringbuf_i2s = xRingbufferCreate(32*1024,RINGBUF_TYPE_BYTEBUF);
#endif
if (s_ringbuf_i2s == NULL) { printf("nospace for ringbuffer\n"); return; }
printf("Ringbuffer ok\n");
xTaskCreate(dsp_i2s_task_handler, "DSP_I2S", 48*1024, NULL, 6, &s_dsp_i2s_task_handle);
}
void dsp_i2s_task_deninit(void)
{ if (s_dsp_i2s_task_handle) {
vTaskDelete(s_dsp_i2s_task_handle);
s_dsp_i2s_task_handle = NULL;
}
if (s_ringbuf_i2s) {
vRingbufferDelete(s_ringbuf_i2s);
s_ringbuf_i2s = NULL;
}
}
size_t write_ringbuf(const uint8_t *data, size_t size)
{
BaseType_t done = xRingbufferSend(s_ringbuf_i2s, (void *)data, size, (portTickType)portMAX_DELAY);
return (done)?size:0;
}
// ESP32 DSP processor
//======================================================
// Each time a buffer of audio is passed to the DSP - samples are
// processed according to a dynamic list of audio processing nodes.
// Each audio processor node consist of a data struct holding the
// required weights and states for processing an automomous processing
// function. The high level parameters is maintained in the structre
// as well
// Release - Prove off concept
// ----------------------------------------
// Fixed 2x2 biquad flow Xover for biAmp systems
// Interface for cross over frequency and level
void dsp_setup_flow(double freq, uint32_t samplerate) {
float f = freq/samplerate/2.;
bq[0] = (ptype_t) { LPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
bq[1] = (ptype_t) { LPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
bq[2] = (ptype_t) { HPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
bq[3] = (ptype_t) { HPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
bq[4] = (ptype_t) { HPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
bq[5] = (ptype_t) { HPF, f, 0, 0.707, NULL, NULL, {0,0,0,0,0}, {0, 0} } ;
pnode_t * aflow = NULL;
aflow = malloc(sizeof(pnode_t));
if (aflow == NULL)
{ printf("Could not create node");
}
for (uint8_t n=0; n<=5; n++)
{ switch (bq[n].filtertype) {
case LPF: dsps_biquad_gen_lpf_f32( bq[n].coeffs, bq[n].freq, bq[n].q );
break;
case HPF: dsps_biquad_gen_hpf_f32( bq[n].coeffs, bq[n].freq, bq[n].q );
break;
default : break;
}
for (uint8_t i = 0;i <=3 ;i++ )
{ printf("%.6f ",bq[n].coeffs[i]);
}
printf("\n");
}
}
void dsp_set_xoverfreq(uint8_t freqh, uint8_t freql,uint32_t samplerate) {
float freq = freqh*256 + freql;
printf("%f\n",freq);
float f = freq/samplerate/2.;
for ( int8_t n=0; n<=5; n++)
{ bq[n].freq = f ;
switch (bq[n].filtertype) {
case LPF:
for (uint8_t i = 0;i <=4 ;i++ )
{ printf("%.6f ",bq[n].coeffs[i]); }
printf("\n");
dsps_biquad_gen_lpf_f32( bq[n].coeffs, bq[n].freq, bq[n].q );
for (uint8_t i = 0;i <=4 ;i++ )
{ printf("%.6f ",bq[n].coeffs[i]); }
printf("%f \n",bq[n].freq);
break;
case HPF:
dsps_biquad_gen_hpf_f32( bq[n].coeffs, bq[n].freq, bq[n].q );
break;
default : break;
}
}
}

36
components/dsp_processor/include/dsp_processor.h
View File

@@ -1,36 +0,0 @@
#ifndef _DSP_PROCESSOR_H_
#define _DSP_PROCESSOR_H_
enum dspFlows {dspfStereo, dspfBiamp, dspf2DOT1, dspfFunkyHonda };
size_t write_ringbuf(const uint8_t *data, size_t size);
void dsp_i2s_task_init(uint32_t sample_rate,bool slave);
void dsp_i2s_task_deinit(void);
enum filtertypes { LPF, HPF, BPF, BPF0DB, NOTCH,
ALLPASS360, ALLPASS180, PEAKINGEQ,
LOWSHELF, HIGHSHELF};
// Process node
typedef struct ptype {
int filtertype;
float freq;
float gain;
float q;
float *in,*out;
float coeffs[5];
float w[2];
} ptype_t;
// Process flow
typedef struct pnode {
ptype_t process;
struct pnode *next;
} pnode_t;
void dsp_setup_flow(double freq,uint32_t samplerate);
void dsp_set_xoverfreq(uint8_t, uint8_t, uint32_t );
#endif /* _DSP_PROCESSOR_H_ */

7
components/esp-dsp/CMakeLists.txt
View File

@@ -1,7 +0,0 @@
idf_component_register(SRCS "dsps_biquad_gen_f32.c"
"dsps_biquad_f32_ae32.S"
"dsps_dotprode_f32_ae32.S"
"dsps_biquad_f32_ansi.c"
"dsps_dotprode_f32_m_ae32.S"
INCLUDE_DIRS "include" )

11
components/esp-dsp/component.mk
View File

@@ -1,11 +0,0 @@
#
# Main Makefile. This is basically the same as a component makefile.
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component_common.mk. By default,
# this will take the sources in the src/ directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the ESP-IDF documents if you need to do this.
#
COMPONENT_SRCDIRS := .
# CFLAGS +=

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components/esp-dsp/dsps_biquad_f32_ae32.S
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@@ -1,86 +0,0 @@
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "./dsps_dotprode_f32_m_ae32.S"
// This is bi quad filter form II for ESP32 processor.
.text
.align 4
.global dsps_biquad_f32_ae32
.type dsps_biquad_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_biquad_f32_ae32(const float* input, float* output, int len, float* coef, float* w)
// {
// for (int i=0 ; i< len ; i++)
// {
// float d0 = input[i] - coef[3]*w[0] - coef[4]*w[1]; (input[i] - a[1]*w[0] - a[2]*w[1];)
// output[i] = coef[0]*d0 + coef[1]*w[0] + coef[2]*w[1];
// w[1] = w[0];
// w[0] = d0;
// }
// return ESP_OK;
// }
dsps_biquad_f32_ae32:
// input - a2
// output - a3
// len - a4
// coeffs - a5
// w- a6
// f0 - b0
// f1 - b1
// f2 - b2
// f3 - a1
// f4 - a2
// f5 - w0
// f6 - w1
entry a1, 16
// Array increment for floating point data should be 4
lsi f0, a5, 0
lsi f1, a5, 4
lsi f2, a5, 8
lsi f3, a5, 12
lsi f4, a5, 16
neg.s f5, f3 // -a[1]
neg.s f6, f4 // -a[2]
lsi f7, a6, 0 // w[0]
lsi f8, a6, 4 // w[1]
addi a3, a3, -4 // i-- // preset a3
lsi f9, a2, 0 // f9 = x[i]
loopnez a4, loop_bq_end_m_ae32
madd.s f9, f7, f5 // f9 += -a1*w0
addi a3, a3, 4 // out++;
mul.s f10, f1, f7 // f10 = b1*w0
madd.s f9, f8, f6 // f9 += -a2*w1
madd.s f10, f9, f0 // f10 += b0*d0
addi a2, a2, 4 // in++;
madd.s f10, f2, f8 // f10+= b2*w1, f10 - result
mov.s f8, f7 // w1 = w0
mov.s f7, f9 // w0 = d0
lsi f9, a2, 0 // f9 = x[i]
ssi f10, a3, 0 // y[i] = result
loop_bq_end_m_ae32:
// Store delay line
ssi f7, a6, 0
ssi f8, a6, 4
movi.n a2, 0 // return status ESP_OK
retw.n

28
components/esp-dsp/dsps_biquad_f32_ansi.c
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad.h"
esp_err_t dsps_biquad_f32_ansi(const float *input, float *output, int len, float *coef, float *w)
{
for (int i = 0 ; i < len ; i++) {
float d0 = input[i] - coef[3] * w[0] - coef[4] * w[1];
output[i] = coef[0] * d0 + coef[1] * w[0] + coef[2] * w[1];
w[1] = w[0];
w[0] = d0;
}
return ESP_OK;
}

290
components/esp-dsp/dsps_biquad_gen_f32.c
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "dsps_biquad_gen.h"
#include <math.h>
#include "esp_log.h"
esp_err_t dsps_biquad_gen_lpf_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = (1 - c) / 2;
float b1 = 1 - c;
float b2 = b0;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_hpf_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = (1 + c) / 2;
float b1 = -(1 + c);
float b2 = b0;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_bpf_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = s / 2;
float b1 = 0;
float b2 = -b0;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_bpf0db_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = alpha;
float b1 = 0;
float b2 = -alpha;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_notch_f32(float *coeffs, float f, float gain, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float A = sqrtf(pow(10, (double)gain / 20.0));
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = 1 + alpha * A;
float b1 = -2 * c;
float b2 = 1 - alpha * A;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_allpass360_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = 1 - alpha;
float b1 = -2 * c;
float b2 = 1 + alpha;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_allpass180_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = 1 - alpha;
float b1 = -2 * c;
float b2 = 1 + alpha;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_peakingEQ_f32(float *coeffs, float f, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = alpha;
float b1 = 0;
float b2 = -alpha;
float a0 = 1 + alpha;
float a1 = -2 * c;
float a2 = 1 - alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_lowShelf_f32(float *coeffs, float f, float gain, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float A = sqrtf(pow(10, (double)gain / 20.0));
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = A * ((A + 1) - (A - 1) * c + 2 * sqrtf(A) * alpha);
float b1 = 2 * A * ((A - 1) - (A + 1) * c);
float b2 = A * ((A + 1) - (A - 1) * c - 2 * sqrtf(A) * alpha);
float a0 = (A + 1) + (A - 1) * c + 2 * sqrtf(A) * alpha;
float a1 = -2 * ((A - 1) + (A + 1) * c);
float a2 = (A + 1) + (A - 1) * c - 2 * sqrtf(A) * alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}
esp_err_t dsps_biquad_gen_highShelf_f32(float *coeffs, float f, float gain, float qFactor)
{
if (qFactor <= 0.0001) {
qFactor = 0.0001;
}
float Fs = 1;
float A = sqrtf(pow(10, (double)gain / 20.0));
float w0 = 2 * M_PI * f / Fs;
float c = cosf(w0);
float s = sinf(w0);
float alpha = s / (2 * qFactor);
float b0 = A * ((A + 1) + (A - 1) * c + 2 * sqrtf(A) * alpha);
float b1 = -2 * A * ((A - 1) + (A + 1) * c);
float b2 = A * ((A + 1) + (A - 1) * c - 2 * sqrtf(A) * alpha);
float a0 = (A + 1) - (A - 1) * c + 2 * sqrtf(A) * alpha;
float a1 = 2 * ((A - 1) - (A + 1) * c);
float a2 = (A + 1) - (A - 1) * c - 2 * sqrtf(A) * alpha;
coeffs[0] = b0 / a0;
coeffs[1] = b1 / a0;
coeffs[2] = b2 / a0;
coeffs[3] = a1 / a0;
coeffs[4] = a2 / a0;
return ESP_OK;
}

59
components/esp-dsp/dsps_dotprode_f32_ae32.S
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "./dsps_dotprode_f32_m_ae32.S"
// This is dot product function for ESP32 processor.
.text
.align 4
.global dsps_dotprode_f32_ae32
.type dsps_dotprode_f32_ae32,@function
// The function implements the following C code:
//esp_err_t dsps_dotprod_f32_ae32(const float* src1, const float* src2, float* dest, int len)
//{
// float acc = 0;
// for (int i=0 ; i< len ; i++)
// {
// acc += src1[i]*src2[i];
// }
// *dest = acc;
// return ESP_OK;
//}
dsps_dotprode_f32_ae32:
// src1 - a2
// src2 - a3
// dest - a4
// len - a5
// step1- a6
// step2- a7
entry a1, 16
// Array increment for floating point data should be 4
slli a6,a6, 2
slli a7,a7, 2
// Clear initial state of the result register
movi.n a9, 0
wfr f1, a9
// a2 - input1
// a3 - input2
// a5 - length
// a6,a7, step in arrays
dotprode_f32_ae32 a2, a3, a5, a6, a7;
ssi f1, a4, 0 // Store result from f1 to memory at a4
movi.n a2, 0 // return status ESP_OK
retw.n

41
components/esp-dsp/dsps_dotprode_f32_m_ae32.S
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
.macro dotprode_f32_ae32 x1 x2 count step1 step2
// This macro calculates floating point dot product for count float samples
// x1, x2 - input arrays
// count - amount of samples
// step1,step2 - A register for array step. (should be divided by 4)
// f1 - contains initial value
//
// result in f1
//
// Macros body:
// f1 += x1[i*step1]*x2[i*step2]; i: 0..counter-1
// affected: f0, f1, f2
// Example: dotprod_f32_ae32 a2 a3 a5 a8 a9
// a8 == 4, step is 4 bytes
// a5 == 32, length of array is 32
//
lsi f0, \x2, 0
sub \x1, \x1, \step1 // To compensate first increment
loopnez \count, loop_mace_end_m_ae32
add.n \x1, \x1, \step1
lsi f2, \x1, 0
madd.s f1, f2, f0
add.n \x2, \x2, \step2
lsi f0, \x2, 0
loop_mace_end_m_ae32:
.endm

42
components/esp-dsp/include/dsp_common.h
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _dsp_common_H_
#define _dsp_common_H_
#include <stdint.h>
#include <stdbool.h>
#include "dsp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief check power of two
* The function check if the argument is power of 2.
* The implementation use ANSI C and could be compiled and run on any platform
*
* @return
* - true if x is power of two
* - false if no
*/
bool dsp_is_power_of_two(int x);
#ifdef __cplusplus
}
#endif
#endif // _dsp_common_H_

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components/esp-dsp/include/dsp_err.h
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DSP_ERR_H_
#define _DSP_ERR_H_
#include "stdint.h"
#include "esp_err.h"
#include "dsp_err_codes.h"
#endif // _DSP_ERR_H_

27
components/esp-dsp/include/dsp_err_codes.h
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@@ -1,27 +0,0 @@
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _dsp_error_codes_H_
#define _dsp_error_codes_H_
#define DSP_OK 0 // For internal use only. Please use ESP_OK instead
#define ESP_ERR_DSP_BASE 0x70000
#define ESP_ERR_DSP_INVALID_LENGTH (ESP_ERR_DSP_BASE + 1)
#define ESP_ERR_DSP_INVALID_PARAM (ESP_ERR_DSP_BASE + 2)
#define ESP_ERR_DSP_PARAM_OUTOFRANGE (ESP_ERR_DSP_BASE + 3)
#define ESP_ERR_DSP_UNINITIALIZED (ESP_ERR_DSP_BASE + 4)
#define ESP_ERR_DSP_REINITIALIZED (ESP_ERR_DSP_BASE + 5)
#endif // _dsp_error_codes_H_

27
components/esp-dsp/include/dsp_tests.h
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DSP_TESTS_H_
#define _DSP_TESTS_H_
#define TEST_ASSERT_EXEC_IN_RANGE(min_exec, max_exec, actual) \
if (cycles >= max_exec) { \
TEST_ASSERT_MESSAGE (false, "Exec time takes more than expected!");\
}\
if (cycles < min_exec) {\
TEST_ASSERT_MESSAGE (false, "Exec time takes less then expected!");\
}
#endif // _DSP_TESTS_H_

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components/esp-dsp/include/dsps_biquad.h
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _dsps_biquad_H_
#define _dsps_biquad_H_
#include "dsp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**@{*/
/**
* @brief IIR filter
*
* IIR filter 2nd order direct form II (bi quad)
* The extension (_ansi) use ANSI C and could be compiled and run on any platform.
* The extension (_ae32) is optimized for ESP32 chip.
*
* @param[in] input: input array
* @param output: output array
* @param len: length of input and output vectors
* @param coef: array of coefficients. b0,b1,b2,a1,a2
* expected that a0 = 1. b0..b2 - numerator, a0..a2 - denominator
* @param w: delay line w0,w1. Length of 2.
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_f32_ansi(const float *input, float *output, int len, float *coef, float *w);
esp_err_t dsps_biquad_f32_ae32(const float *input, float *output, int len, float *coef, float *w);
/**@}*/
#ifdef __cplusplus
}
#endif
#ifdef CONFIG_DSP_OPTIMIZED
#define dsps_biquad_f32 dsps_biquad_f32_ae32
#endif
#ifdef CONFIG_DSP_ANSI
#define dsps_biquad_f32 dsps_biquad_f32_ansi
#endif
#endif // _dsps_biquad_H_

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components/esp-dsp/include/dsps_biquad_gen.h
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// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _dsps_biquad_gen_H_
#define _dsps_biquad_gen_H_
#include "dsp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
// Common rules for all generated coefficients.
// The coefficients placed to the array as follows:
// coeffs[0] = b0;
// coeffs[1] = b1;
// coeffs[2] = b2;
// coeffs[3] = a1;
// coeffs[4] = a2;
// a0 - are not placed and expected always as == 1
/**
* @brief LPF IIR filter coefficients
* Coefficients for low pass 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter cut off frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_lpf_f32(float *coeffs, float f, float qFactor);
/**
* @brief HPF IIR filter coefficients
*
* Coefficients for high pass 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter cut off frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_hpf_f32(float *coeffs, float f, float qFactor);
/**
* @brief BPF IIR filter coefficients
*
* Coefficients for band pass 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter center frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_bpf_f32(float *coeffs, float f, float qFactor);
/**
* @brief 0 dB BPF IIR filter coefficients
*
* Coefficients for band pass 2nd order IIR filter (bi-quad) with 0 dB gain in passband
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter center frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_bpf0db_f32(float *coeffs, float f, float qFactor);
/**
* @brief Notch IIR filter coefficients
*
* Coefficients for notch 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param gain: gain in stopband in dB
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_notch_f32(float *coeffs, float f, float gain, float qFactor);
/**
* @brief Allpass 360 degree IIR filter coefficients
*
* Coefficients for all pass 2nd order IIR filter (bi-quad) with 360 degree phase shift
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_allpass360_f32(float *coeffs, float f, float qFactor);
/**
* @brief Allpass 180 degree IIR filter coefficients
*
* Coefficients for all pass 2nd order IIR filter (bi-quad) with 180 degree phase shift
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_allpass180_f32(float *coeffs, float f, float qFactor);
/**
* @brief peak IIR filter coefficients
*
* Coefficients for peak 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_peakingEQ_f32(float *coeffs, float f, float qFactor);
/**
* @brief low shelf IIR filter coefficients
*
* Coefficients for low pass Shelf 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param gain: gain in stopband in dB
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_lowShelf_f32(float *coeffs, float f, float gain, float qFactor);
/**
* @brief high shelf IIR filter coefficients
*
* Coefficients for high pass Shelf 2nd order IIR filter (bi-quad)
* The implementation use ANSI C and could be compiled and run on any platform
*
* @param coeffs: result coefficients. b0,b1,b2,a1,a2, a0 are not placed to the array and expected by IIR as 1
* @param f: filter notch frequency in range of 0..0.5 (normalized to sample frequency)
* @param gain: gain in stopband in dB
* @param qFactor: Q factor of filter
*
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_biquad_gen_highShelf_f32(float *coeffs, float f, float gain, float qFactor);
#ifdef __cplusplus
}
#endif
#endif // _dsps_biquad_gen_H_

105
components/esp-dsp/include/dsps_dotprod.h
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@@ -1,105 +0,0 @@
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DSPI_DOTPROD_H_
#define _DSPI_DOTPROD_H_
#include "esp_log.h"
#include "dsp_err.h"
#ifdef __cplusplus
extern "C"
{
#endif
// These functions calculates dotproduct of two vectors.
/**@{*/
/**
* @brief dot product of two 16 bit vectors
* Dot product calculation for two signed 16 bit arrays: *dest += (src1[i] * src2[i]) >> (15-shift); i= [0..N)
* The extension (_ansi) use ANSI C and could be compiled and run on any platform.
* The extension (_ae32) is optimized for ESP32 chip.
*
* @param[in] src1 source array 1
* @param[in] src2 source array 2
* @param dest destination pointer
* @param[in] len length of input arrays
* @param[in] shift shift of the result.
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_dotprod_s16_ansi(const int16_t *src1, const int16_t *src2, int16_t *dest, int len, int8_t shift);
esp_err_t dsps_dotprod_s16_ae32(const int16_t *src1, const int16_t *src2, int16_t *dest, int len, int8_t shift);
/**@}*/
/**@{*/
/**
* @brief dot product of two float vectors
* Dot product calculation for two floating point arrays: *dest += (src1[i] * src2[i]); i= [0..N)
* The extension (_ansi) use ANSI C and could be compiled and run on any platform.
* The extension (_ae32) is optimized for ESP32 chip.
*
* @param[in] src1 source array 1
* @param[in] src2 source array 2
* @param dest destination pointer
* @param[in] len length of input arrays
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_dotprod_f32_ansi(const float *src1, const float *src2, float *dest, int len);
esp_err_t dsps_dotprod_f32_ae32(const float *src1, const float *src2, float *dest, int len);
/**@}*/
/**@{*/
/**
* @brief dot product of two float vectors with step
* Dot product calculation for two floating point arrays: *dest += (src1[i*step1] * src2[i*step2]); i= [0..N)
* The extension (_ansi) use ANSI C and could be compiled and run on any platform.
* The extension (_ae32) is optimized for ESP32 chip.
*
* @param[in] src1 source array 1
* @param[in] src2 source array 2
* @param dest destination pointer
* @param[in] len length of input arrays
* @param[in] step1 step over elements in first array
* @param[in] step2 step over elements in second array
* @return
* - ESP_OK on success
* - One of the error codes from DSP library
*/
esp_err_t dsps_dotprode_f32_ansi(const float *src1, const float *src2, float *dest, int len, int step1, int step2);
esp_err_t dsps_dotprode_f32_ae32(const float *src1, const float *src2, float *dest, int len, int step1, int step2);
/**@}*/
#ifdef __cplusplus
}
#endif
#ifdef CONFIG_DSP_OPTIMIZED
#define dsps_dotprod_s16 dsps_dotprod_s16_ae32
#define dsps_dotprod_f32 dsps_dotprod_f32_ae32
#define dsps_dotprode_f32 dsps_dotprode_f32_ae32
#endif
#ifdef CONFIG_DSP_ANSI
#define dsps_dotprod_s16 dsps_dotprod_s16_ansi
#define dsps_dotprod_f32 dsps_dotprod_f32_ansi
#define dsps_dotprode_f32 dsps_dotprode_f32_ansi
#endif
#endif // _DSPI_DOTPROD_H_

55
components/esp-dsp/include/esp_dsp.h
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@@ -1,55 +0,0 @@
// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _esp_dsp_H_
#define _esp_dsp_H_
#ifdef __cplusplus
extern "C"
{
#endif
// Common includes
#include "dsp_common.h"
// Signal processing
#include "dsps_dotprod.h"
#include "dsps_fir.h"
#include "dsps_biquad.h"
#include "dsps_biquad_gen.h"
#include "dsps_addc.h"
#include "dsps_mulc.h"
#include "dsps_wind_hann.h"
#include "dsps_d_gen.h"
#include "dsps_h_gen.h"
#include "dsps_tone_gen.h"
#include "dsps_snr.h"
#include "dsps_sfdr.h"
#include "dsps_fft2r.h"
// Matrix operations
#include "dspm_mult.h"
// Support functions
#include "dsps_view.h"
#ifdef __cplusplus
}
#endif
#endif // _esp_dsp_H_

15
components/lightsnapcast/snapcast.c
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@@ -13,6 +13,12 @@
#include <stddef.h>
#include <buffer.h>
#include "esp_log.h"
#include "esp_heap_caps.h"
/* Logging tag */
static const char *TAG = "libSNAPCAST";
const int BASE_MESSAGE_SIZE = 26;
const int TIME_MESSAGE_SIZE = 8;
@@ -260,7 +266,11 @@ int wire_chunk_message_deserialize(wire_chunk_message_t *msg, const char *data,
}
// TODO maybe should check to see if need to free memory?
#if CONFIG_SPIRAM
msg->payload = (char *)heap_caps_malloc(msg->size * sizeof(char), MALLOC_CAP_SPIRAM);
#else
msg->payload = malloc(msg->size * sizeof(char));
#endif
// Failed to allocate the memory
if (!msg->payload) {
return 2;
@@ -306,4 +316,7 @@ int time_message_deserialize(time_message_t *msg, const char *data, uint32_t siz
result |= buffer_read_int32(&buffer, &(msg->latency.usec));
return result;
}
}

20
components/opus/CMakeLists.txt
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@@ -1,20 +0,0 @@
file(GLOB srcs "opus/src/*.c")
file(GLOB silk "opus/silk/*.c")
file(GLOB celt "opus/celt/*.c")
file(GLOB fixed "opus/slik/fixed/*.c")
file(GLOB float "opus/slik/float/*.c")
idf_component_register(SRCS "${srcs}" "${silk}" "${celt}" "${fixed}" "${float}"
INCLUDE_DIRS .
"opus/include"
"opus/silk"
"opus/silk/fixed"
"opus/silk/float"
"opus/celt"
)
target_compile_definitions(${COMPONENT_TARGET} PRIVATE "-DHAVE_CONFIG_H")

12
components/opus/component.mk
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@@ -1,12 +0,0 @@
#
# Main Makefile. This is basically the same as a component makefile.
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component_common.mk. By default,
# this will take the sources in the src/ directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the ESP-IDF documents if you need to do this.
#
COMPONENT_SRCDIRS := opus/src opus/silk opus/silk/fixed opus/celt
COMPONENT_ADD_INCLUDEDIRS := . opus/include opus/silk opus/silk/fixed opus/celt
CFLAGS += -DHAVE_CONFIG_H

208
components/opus/config.h
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@@ -1,208 +0,0 @@
/* config.h. Generated from config.h.in by configure. */
/* config.h.in. Generated from configure.ac by autoheader. */
/* Get CPU Info by asm method */
/* #undef CPU_INFO_BY_ASM */
/* Get CPU Info by c method */
/* #undef CPU_INFO_BY_C */
/* Custom modes */
/* #undef CUSTOM_MODES */
/* Do not build the float API */
//#define DISABLE_FLOAT_API 1
/* Assertions */
/* #undef ENABLE_ASSERTIONS */
/* Ambisonics Support */
/* #undef ENABLE_EXPERIMENTAL_AMBISONICS */
/* Enable bitstream changes from draft-ietf-codec-opus-update */
/* #undef ENABLE_UPDATE_DRAFT */
/* Debug fixed-point implementation */
/* #undef FIXED_DEBUG */
/* Compile as fixed-point (for machines without a fast enough FPU) */
#define FIXED_POINT 1
/* Float approximations */
/* #undef FLOAT_APPROX */
/* Fuzzing */
/* #undef FUZZING */
/* Define to 1 if you have the <alloca.h> header file. */
/* #undef HAVE_ALLOCA_H */
/* NE10 library is installed on host. Make sure it is on target! */
/* #undef HAVE_ARM_NE10 */
/* Define to 1 if you have the <dlfcn.h> header file. */
/* #undef HAVE_DLFCN_H */
#define HAVE_DLFCN_H 1
/* Define to 1 if you have the <inttypes.h> header file. */
#define HAVE_INTTYPES_H 1
/* Define to 1 if you have the `lrint' function. */
/* #undef HAVE_LRINT */
#define HAVE_LRINT 1
/* Define to 1 if you have the `lrintf' function. */
/* #undef HAVE_LRINTF */
#define HAVE_LRINTF 1
/* Define to 1 if you have the <memory.h> header file. */
/* #undef HAVE_MEMORY_H */
#define HAVE_MEMORY_H 1
/* Define to 1 if you have the <stdint.h> header file. */
#define HAVE_STDINT_H 1
/* Define to 1 if you have the <stdlib.h> header file. */
#define HAVE_STDLIB_H 1
/* Define to 1 if you have the <strings.h> header file. */
#define HAVE_STRINGS_H 1
/* Define to 1 if you have the <string.h> header file. */
#define HAVE_STRING_H 1
/* Define to 1 if you have the <sys/stat.h> header file. */
#define HAVE_SYS_STAT_H 1
/* Define to 1 if you have the <sys/types.h> header file. */
#define HAVE_SYS_TYPES_H 1
/* Define to 1 if you have the <unistd.h> header file. */
#define HAVE_UNISTD_H 1
/* Define to 1 if you have the `__malloc_hook' function. */
/* #undef HAVE___MALLOC_HOOK */
/* Define to the sub-directory where libtool stores uninstalled libraries. */
#define LT_OBJDIR ".libs/"
/* Make use of ARM asm optimization */
/* #undef OPUS_ARM_ASM */
/* Use generic ARMv4 inline asm optimizations */
/* #undef OPUS_ARM_INLINE_ASM */
/* Use ARMv5E inline asm optimizations */
/* #undef OPUS_ARM_INLINE_EDSP */
/* Use ARMv6 inline asm optimizations */
/* #undef OPUS_ARM_INLINE_MEDIA */
/* Use ARM NEON inline asm optimizations */
/* #undef OPUS_ARM_INLINE_NEON */
/* Define if assembler supports EDSP instructions */
/* #undef OPUS_ARM_MAY_HAVE_EDSP */
/* Define if assembler supports ARMv6 media instructions */
/* #undef OPUS_ARM_MAY_HAVE_MEDIA */
/* Define if compiler supports NEON instructions */
/* #undef OPUS_ARM_MAY_HAVE_NEON */
/* Compiler supports ARMv7/Aarch64 Neon Intrinsics */
/* #undef OPUS_ARM_MAY_HAVE_NEON_INTR */
/* Define if binary requires Aarch64 Neon Intrinsics */
/* #undef OPUS_ARM_PRESUME_AARCH64_NEON_INTR */
/* Define if binary requires EDSP instruction support */
/* #undef OPUS_ARM_PRESUME_EDSP */
/* Define if binary requires ARMv6 media instruction support */
/* #undef OPUS_ARM_PRESUME_MEDIA */
/* Define if binary requires NEON instruction support */
/* #undef OPUS_ARM_PRESUME_NEON */
/* Define if binary requires NEON intrinsics support */
/* #undef OPUS_ARM_PRESUME_NEON_INTR */
/* This is a build of OPUS */
#define OPUS_BUILD /**/
/* Run bit-exactness checks between optimized and c implementations */
/* #undef OPUS_CHECK_ASM */
/* Use run-time CPU capabilities detection */
/* #undef OPUS_HAVE_RTCD */
/* Compiler supports X86 AVX Intrinsics */
/* #undef OPUS_X86_MAY_HAVE_AVX */
/* Compiler supports X86 SSE Intrinsics */
/* #undef OPUS_X86_MAY_HAVE_SSE */
/* Compiler supports X86 SSE2 Intrinsics */
/* #undef OPUS_X86_MAY_HAVE_SSE2 */
/* Compiler supports X86 SSE4.1 Intrinsics */
/* #undef OPUS_X86_MAY_HAVE_SSE4_1 */
/* Define if binary requires AVX intrinsics support */
/* #undef OPUS_X86_PRESUME_AVX */
/* Define if binary requires SSE intrinsics support */
/* #undef OPUS_X86_PRESUME_SSE */
/* Define if binary requires SSE2 intrinsics support */
/* #undef OPUS_X86_PRESUME_SSE2 */
/* Define if binary requires SSE4.1 intrinsics support */
/* #undef OPUS_X86_PRESUME_SSE4_1 */
/* Define to the address where bug reports for this package should be sent. */
#define PACKAGE_BUGREPORT "opus@xiph.org"
/* Define to the full name of this package. */
#define PACKAGE_NAME "opus"
/* Define to the full name and version of this package. */
#define PACKAGE_STRING "opus 1.3.1"
/* Define to the one symbol short name of this package. */
#define PACKAGE_TARNAME "opus"
/* Define to the home page for this package. */
#define PACKAGE_URL ""
/* Define to the version of this package. */
#define PACKAGE_VERSION "1.3.1"
/* Define to 1 if you have the ANSI C header files. */
#define STDC_HEADERS 1
/* Make use of alloca */
/* #undef USE_ALLOCA */
/* Use C99 variable-size arrays */
#define VAR_ARRAYS 1
/* Define to empty if `const' does not conform to ANSI C. */
/* #undef const */
/* Define to `__inline__' or `__inline' if that's what the C compiler
calls it, or to nothing if 'inline' is not supported under any name. */
#ifndef __cplusplus
/* #undef inline */
#endif
/* Define to the equivalent of the C99 'restrict' keyword, or to
nothing if this is not supported. Do not define if restrict is
supported directly. */
#define restrict __restrict
/* Work around a bug in Sun C++: it does not support _Restrict or
__restrict__, even though the corresponding Sun C compiler ends up with
"#define restrict _Restrict" or "#define restrict __restrict__" in the
previous line. Perhaps some future version of Sun C++ will work with
restrict; if so, hopefully it defines __RESTRICT like Sun C does. */
#if defined __SUNPRO_CC && !defined __RESTRICT
# define _Restrict
# define __restrict__
#endif

1
components/opus/opus

Submodule components/opus/opus deleted from 8aa7767207

3
components/rtprx/CMakeLists.txt
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@@ -1,3 +0,0 @@
idf_component_register(SRCS "rtprx.c"
INCLUDE_DIRS "include"
REQUIRES opus)

12
components/rtprx/component.mk
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@@ -1,12 +0,0 @@
#
# Main Makefile. This is basically the same as a component makefile.
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component_common.mk. By default,
# this will take the sources in the src/ directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the ESP-IDF documents if you need to do this.
#
COMPONENT_SRCDIRS := .
# CFLAGS +=

11
components/rtprx/include/rtprx.h
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@@ -1,11 +0,0 @@
#ifndef _RTPRX_H_
#define _RTPRX_H_
void rtp_rx_start(void);
void rtp_rx_stop(void);
void rtp_rx_task(void *pvParameters);
void setup_rtp_i2s();
#endif /* _RTPRX_H_ */

169
components/rtprx/rtprx.c
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@@ -1,169 +0,0 @@
/**
* \file rtprx.c
* \author Jorgen Kragh Jakobsen
* \date 19.10.2019
* \version 0.1
*
* \brief RTP audio stream reciever
*
* \warning This software is a PROTOTYPE version and is not designed or intended for use in production, especially not for safety-critical applications!
* The user represents and warrants that it will NOT use or redistribute the Software for such purposes.
* This prototype is for research purposes only. This software is provided "AS IS," without a warranty of any kind.
*/
#include "rtprx.h"
#include "freertos/FreeRTOS.h"
#include "esp_log.h"
#include "esp_wifi.h"
#include "esp_netif.h"
#include "lwip/api.h"
#include "lwip/err.h"
#include "lwip/sockets.h"
#include "lwip/sys.h"
#include <lwip/netdb.h>
#include "driver/i2s.h"
#include "opus.h"
//extern uint32_t sample_rate = 48000; xxx fixme
static bool rtpRxState = 0;
void rtp_rx_start() {
if (rtpRxState == 0 )
{ setup_rtp_i2s();
xTaskCreate(rtp_rx_task, "RTPRx", 12*1024, NULL, 0, NULL);
rtpRxState = 1;
}
}
void rtp_rx_stop() {
if (rtpRxState == 1)
{ i2s_driver_uninstall(0);
//vTaskDelete(xTaskSignal); xxx Fix me
rtpRxState = 0;
}
}
void rtp_rx_task(void *pvParameters){
OpusDecoder *decoder;
//int size = opus_decoder_get_size(2);
int oe = 0;
decoder = opus_decoder_create(48000,2,&oe);
// int error = opus_decoder_init(decoder, 48000, 2);
printf("Initialized Decoder: %d", oe);
//int32_t *audio32 = (int32_t*)malloc(960*sizeof(int32_t));
int16_t *audio = (int16_t *)malloc(960*2*sizeof(int16_t));
i2s_zero_dma_buffer(0);
static struct netconn *conn;
static struct netbuf *buf;
static uint32_t pkg = 0 ;
static uint32_t pkgerror = 0;
err_t err;
uint16_t oldseq = 1;
uint16_t first = 1;
conn = netconn_new(NETCONN_UDP);
if (conn!=NULL)
{ printf("Net RTP RX\n");
netconn_bind(conn, IP_ADDR_ANY, 1350);
netconn_listen(conn);
printf("Net RTP will enter loopn\n");
while (1) {
netconn_recv(conn,&buf);
if (buf == NULL)
{ printf("NETCONN RX error \n"); }
pkg++;
uint8_t *p = (buf->p->payload);
uint16_t seq = (p[2]<<8)+p[3];
if ( (seq!=oldseq+1) & (first != 1) )
{ printf("seq : %d, oldseq : %d \n",seq,oldseq);
uint16_t errors = seq-oldseq-1;
pkgerror = pkgerror + errors;
printf("ERROR --- Package drop : %d %d \n",errors, pkgerror);
size_t bWritten;
//for (int i = 0; i;i++ )
int ret = i2s_write_expand(0, (char*)audio, 960*2*sizeof(int16_t),16,32, &bWritten, 100);
printf("bWritten : %d ret : %d \n ",bWritten,ret);
//opus_pkg = NULL;
}
if (seq<oldseq)
{ printf("ERROR --- Packege order:"); }
oldseq = seq;
first = 0;
//printf("UDP package len : %d -> \n", buf->p->len);
//printf("UDP package : %02x %02x %02x %02x\n",p[0],p[1],p[2],p[3]);
//printf("Timestamp : %02x %02x %02x %02x\n",p[4],p[5],p[6],p[7]);
//printf("Sync source : %02x %02x %02x %02x\n",p[8],p[9],p[10],p[11]);
//printf("R1 : %d \n",(p[12]&0xf8)>>3) ;
//int size = 240;
unsigned char *opus_pkg = buf->p->payload + 12;
int size = opus_decode(decoder, (unsigned char *)opus_pkg, buf->p->len-12, (opus_int16*)audio, 960, 0);
if (size < 0 )
{ printf("Decode error : %d \n",size); }
//for (int i = 0; i < size*2; i++) {
// audio[i*2] = 0x0000;
// audio[i*2+1] = 0x0000;
//}
size_t bWritten;
int ret = i2s_write_expand(0, (char*)audio, size*2*sizeof(int16_t),16,32, &bWritten, 100);
if (ret != 0 ) printf("Error I2S written: %d %d %d \n",ret, size*2*sizeof(int16_t) ,bWritten);
if ((pkg%1000)==1) {
//printf("I2S written: %d %d \n", size*sizeof(int32_t) ,bWritten);
printf("%d > %d %d %d\n",pkg, size, buf->p->len, buf->p->tot_len );
printf("UDP package len : %d -> \n", buf->p->len);
printf("UDP package : %02x %02x %02x %02x\n",p[0],p[1],p[2],p[3]);
printf("Timestamp : %02x %02x %02x %02x\n",p[4],p[5],p[6],p[7]);
printf("Sync source : %02x %02x %02x %02x\n",p[8],p[9],p[10],p[11]);
printf("R1 : %d \n",(p[12]&0xf8)>>3) ;
for (int i=0;i<8;i++)
printf("%02d %04x %04x\n",i,audio[2*i],audio[2*i+1]);
}
//netbuf_free(buf);
netbuf_delete(buf);
}
}
netconn_close(conn);
netconn_delete(conn);
}
void setup_rtp_i2s()
{
i2s_config_t i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX, // Only TX
.sample_rate = 48000,
.bits_per_sample = 32,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S,
.dma_buf_count = 8,
.dma_buf_len = 480,
//.intr_alloc_flags = 1, //Default interrupt priority
.use_apll = true,
.fixed_mclk = 0,
.tx_desc_auto_clear = true //Auto clear tx descriptor on underflow
};
i2s_driver_install(0, &i2s_config, 0, NULL);
i2s_zero_dma_buffer(0);
i2s_pin_config_t pin_config = {
.bck_io_num = 12, //CONFIG_EXAMPLE_I2S_BCK_PIN,
.ws_io_num = 13, //CONFIG_EXAMPLE_I2S_LRCK_PIN,
.data_out_num = 14, //CONFIG_EXAMPLE_I2S_DATA_PIN,
.data_in_num = -1 //Not used
};
i2s_set_pin(0, &pin_config);
printf("Here... set pin\n");
}

10
main/CMakeLists.txt
View File

@@ -1,2 +1,8 @@
idf_component_register(SRCS "main.c"
INCLUDE_DIRS ".")
# Edit following two lines to set component requirements (see docs)
set(COMPONENT_REQUIRES )
set(COMPONENT_PRIV_REQUIRES )
set(COMPONENT_SRCS "main.c")
set(COMPONENT_ADD_INCLUDEDIRS "")
register_component()

14
main/Kconfig.projbuild Normal file
View File

@@ -0,0 +1,14 @@
# put here your custom config value
menu "Access Point configuration"
config ESP_WIFI_SSID
string "WiFi SSID"
default "myssid"
help
SSID (network name) for the example to connect to.
config ESP_WIFI_PASSWORD
string "WiFi Password"
default "mypassword"
help
WiFi password (WPA or WPA2) for the example to use.
endmenu

4
main/component.mk
View File

@@ -1,4 +0,0 @@
#
# "main" pseudo-component makefile.
#
# (Uses default behaviour of compiling all source files in directory, adding 'include' to include path.)

1155
main/main.c
View File

File diff suppressed because it is too large Load Diff

76
sdkconfig
View File

@@ -36,9 +36,9 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
#
# Bootloader config
#
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
@@ -83,11 +83,11 @@ CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
CONFIG_ESPTOOLPY_FLASHFREQ="40m"
# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE="2MB"
CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
CONFIG_ESPTOOLPY_BEFORE_RESET=y
# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
@@ -119,30 +119,11 @@ CONFIG_PARTITION_TABLE_MD5=y
# end of Partition Table
#
# Merus MA120x0 interface Configuration
# Access Point configuration
#
CONFIG_MA120X0_NENABLE_PIN=16
CONFIG_MA120X0_NMUTE_PIN=2
CONFIG_MA120X0_ENABLE_PIN=16
CONFIG_MA120X0_NERR_PIN=21
CONFIG_MA120X0_NCLIP_PIN=22
CONFIG_MA120X0_SCL_PIN=0
CONFIG_MA120X0_SDA_PIN=4
CONFIG_MA120X0_I2C_ADDR=0x20
# end of Merus MA120x0 interface Configuration
#
# ESP32 audio buffer and I2S pin config
#
CONFIG_USE_PSRAM=y
CONFIG_BITS_PER_SAMPLE=16
CONFIG_MASTER_I2S_BCK_PIN=5
CONFIG_MASTER_I2S_LRCK_PIN=25
CONFIG_MASTER_I2S_DATAOUT_PIN=26
CONFIG_SLAVE_I2S_BCK_PIN=35
CONFIG_SLAVE_I2S_LRCK_PIN=12
CONFIG_SLAVE_I2S_DATAOUT_PIN=15
# end of ESP32 audio buffer and I2S pin config
CONFIG_ESP_WIFI_SSID=""
CONFIG_ESP_WIFI_PASSWORD=""
# end of Access Point configuration
#
# Audio HAL
@@ -181,9 +162,10 @@ CONFIG_SR_WN5_HILEXIN=y
# CONFIG_SR_WN5X3_HIJESON is not set
# CONFIG_SR_WN5X3_NIHAOXIAOXIN is not set
# CONFIG_SR_WN5_CUSTOMIZED_WORD is not set
CONFIG_SR_MN1_MODEL_QUANT=y
CONFIG_SR_MN1_CHINESE=y
# CONFIG_SR_MN1_ENGLISH is not set
CONFIG_SINGLE_RECOGNITION=y
# CONFIG_CONTINUOUS_RECOGNITION is not set
CONFIG_SR_CHINESE=y
# CONFIG_SR_ENGLISH is not set
CONFIG_SPEECH_COMMANDS_NUM=20
#
@@ -199,9 +181,9 @@ CONFIG_CN_SPEECH_COMMAND_ID6="zhi re mo shi"
CONFIG_CN_SPEECH_COMMAND_ID7="zhi leng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID8="song feng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID9="jie neng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID10="guan bi jie neng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID11="chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID12="guan bi chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID10="chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID11="jian kang mo shi"
CONFIG_CN_SPEECH_COMMAND_ID12="shui mian mo shi"
CONFIG_CN_SPEECH_COMMAND_ID13="da kai lan ya"
CONFIG_CN_SPEECH_COMMAND_ID14="guan bi lan ya"
CONFIG_CN_SPEECH_COMMAND_ID15="bo fang ge qu"
@@ -418,9 +400,9 @@ CONFIG_ESP32_REV_MIN_0=y
CONFIG_ESP32_REV_MIN=0
CONFIG_ESP32_DPORT_WORKAROUND=y
# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
CONFIG_ESP32_DEFAULT_CPU_FREQ_160=y
# CONFIG_ESP32_DEFAULT_CPU_FREQ_240 is not set
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=160
CONFIG_ESP32_SPIRAM_SUPPORT=y
#
@@ -437,7 +419,7 @@ CONFIG_SPIRAM_BOOT_INIT=y
# CONFIG_SPIRAM_USE_MEMMAP is not set
# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
CONFIG_SPIRAM_USE_MALLOC=y
CONFIG_SPIRAM_MEMTEST=y
# CONFIG_SPIRAM_MEMTEST is not set
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
@@ -580,7 +562,7 @@ CONFIG_ETH_DMA_BUFFER_SIZE=512
CONFIG_ETH_DMA_RX_BUFFER_NUM=10
CONFIG_ETH_DMA_TX_BUFFER_NUM=10
CONFIG_ETH_USE_SPI_ETHERNET=y
# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set
CONFIG_ETH_SPI_ETHERNET_DM9051=y
# CONFIG_ETH_USE_OPENETH is not set
# end of Ethernet
@@ -724,8 +706,7 @@ CONFIG_FMB_SERIAL_BUF_SIZE=256
CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
CONFIG_FMB_SERIAL_TASK_PRIO=10
CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
# CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set
CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
@@ -743,7 +724,7 @@ CONFIG_FMB_TIMER_INDEX=0
CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
CONFIG_FREERTOS_CORETIMER_0=y
# CONFIG_FREERTOS_CORETIMER_1 is not set
CONFIG_FREERTOS_HZ=100
CONFIG_FREERTOS_HZ=1000
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
@@ -860,7 +841,7 @@ CONFIG_LWIP_TCP_TMR_INTERVAL=250
CONFIG_LWIP_TCP_MSL=60000
CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
CONFIG_LWIP_TCP_WND_DEFAULT=5744
CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
CONFIG_LWIP_TCP_RECVMBOX_SIZE=10
CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
# CONFIG_LWIP_TCP_SACK_OUT is not set
# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
@@ -876,7 +857,7 @@ CONFIG_LWIP_MAX_UDP_PCBS=16
CONFIG_LWIP_UDP_RECVMBOX_SIZE=6
# end of UDP
CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=6000
CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set
@@ -1271,8 +1252,7 @@ CONFIG_MB_QUEUE_LENGTH=20
CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
CONFIG_MB_SERIAL_BUF_SIZE=256
CONFIG_MB_SERIAL_TASK_PRIO=10
CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set
CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
CONFIG_MB_CONTROLLER_STACK_SIZE=4096
@@ -1296,14 +1276,14 @@ CONFIG_TCP_MSS=1440
CONFIG_TCP_MSL=60000
CONFIG_TCP_SND_BUF_DEFAULT=5744
CONFIG_TCP_WND_DEFAULT=5744
CONFIG_TCP_RECVMBOX_SIZE=6
CONFIG_TCP_RECVMBOX_SIZE=10
CONFIG_TCP_QUEUE_OOSEQ=y
# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
CONFIG_TCP_OVERSIZE_MSS=y
# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
# CONFIG_TCP_OVERSIZE_DISABLE is not set
CONFIG_UDP_RECVMBOX_SIZE=6
CONFIG_TCPIP_TASK_STACK_SIZE=3072
CONFIG_TCPIP_TASK_STACK_SIZE=6000
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set

216
sdkconfig.old
View File

@@ -36,9 +36,9 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
#
# Bootloader config
#
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF=y
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
@@ -83,11 +83,11 @@ CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
CONFIG_ESPTOOLPY_FLASHFREQ="40m"
# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE="2MB"
CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
CONFIG_ESPTOOLPY_BEFORE_RESET=y
# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
@@ -119,30 +119,11 @@ CONFIG_PARTITION_TABLE_MD5=y
# end of Partition Table
#
# Merus MA120x0 interface Configuration
# Access Point configuration
#
CONFIG_MA120X0_NENABLE_PIN=16
CONFIG_MA120X0_NMUTE_PIN=2
CONFIG_MA120X0_ENABLE_PIN=16
CONFIG_MA120X0_NERR_PIN=21
CONFIG_MA120X0_NCLIP_PIN=22
CONFIG_MA120X0_SCL_PIN=0
CONFIG_MA120X0_SDA_PIN=4
CONFIG_MA120X0_I2C_ADDR=0x20
# end of Merus MA120x0 interface Configuration
#
# ESP32 audio buffer and I2S pin config
#
CONFIG_USE_PSRAM=y
CONFIG_BITS_PER_SAMPLE=32
CONFIG_MASTER_I2S_BCK_PIN=23
CONFIG_MASTER_I2S_LRCK_PIN=13
CONFIG_MASTER_I2S_DATAOUT_PIN=14
CONFIG_SLAVE_I2S_BCK_PIN=26
CONFIG_SLAVE_I2S_LRCK_PIN=12
CONFIG_SLAVE_I2S_DATAOUT_PIN=5
# end of ESP32 audio buffer and I2S pin config
CONFIG_ESP_WIFI_SSID="zuhause"
CONFIG_ESP_WIFI_PASSWORD="dErtischlEr"
# end of Access Point configuration
#
# Audio HAL
@@ -181,9 +162,10 @@ CONFIG_SR_WN5_HILEXIN=y
# CONFIG_SR_WN5X3_HIJESON is not set
# CONFIG_SR_WN5X3_NIHAOXIAOXIN is not set
# CONFIG_SR_WN5_CUSTOMIZED_WORD is not set
CONFIG_SR_MN1_MODEL_QUANT=y
CONFIG_SR_MN1_CHINESE=y
# CONFIG_SR_MN1_ENGLISH is not set
CONFIG_SINGLE_RECOGNITION=y
# CONFIG_CONTINUOUS_RECOGNITION is not set
CONFIG_SR_CHINESE=y
# CONFIG_SR_ENGLISH is not set
CONFIG_SPEECH_COMMANDS_NUM=20
#
@@ -199,9 +181,9 @@ CONFIG_CN_SPEECH_COMMAND_ID6="zhi re mo shi"
CONFIG_CN_SPEECH_COMMAND_ID7="zhi leng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID8="song feng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID9="jie neng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID10="guan bi jie neng mo shi"
CONFIG_CN_SPEECH_COMMAND_ID11="chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID12="guan bi chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID10="chu shi mo shi"
CONFIG_CN_SPEECH_COMMAND_ID11="jian kang mo shi"
CONFIG_CN_SPEECH_COMMAND_ID12="shui mian mo shi"
CONFIG_CN_SPEECH_COMMAND_ID13="da kai lan ya"
CONFIG_CN_SPEECH_COMMAND_ID14="guan bi lan ya"
CONFIG_CN_SPEECH_COMMAND_ID15="bo fang ge qu"
@@ -418,9 +400,9 @@ CONFIG_ESP32_REV_MIN_0=y
CONFIG_ESP32_REV_MIN=0
CONFIG_ESP32_DPORT_WORKAROUND=y
# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
CONFIG_ESP32_DEFAULT_CPU_FREQ_160=y
# CONFIG_ESP32_DEFAULT_CPU_FREQ_240 is not set
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=160
CONFIG_ESP32_SPIRAM_SUPPORT=y
#
@@ -580,7 +562,7 @@ CONFIG_ETH_DMA_BUFFER_SIZE=512
CONFIG_ETH_DMA_RX_BUFFER_NUM=10
CONFIG_ETH_DMA_TX_BUFFER_NUM=10
CONFIG_ETH_USE_SPI_ETHERNET=y
# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set
CONFIG_ETH_SPI_ETHERNET_DM9051=y
# CONFIG_ETH_USE_OPENETH is not set
# end of Ethernet
@@ -724,8 +706,7 @@ CONFIG_FMB_SERIAL_BUF_SIZE=256
CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
CONFIG_FMB_SERIAL_TASK_PRIO=10
CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
# CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set
CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
@@ -743,7 +724,7 @@ CONFIG_FMB_TIMER_INDEX=0
CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
CONFIG_FREERTOS_CORETIMER_0=y
# CONFIG_FREERTOS_CORETIMER_1 is not set
CONFIG_FREERTOS_HZ=100
CONFIG_FREERTOS_HZ=1000
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
@@ -860,7 +841,7 @@ CONFIG_LWIP_TCP_TMR_INTERVAL=250
CONFIG_LWIP_TCP_MSL=60000
CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
CONFIG_LWIP_TCP_WND_DEFAULT=5744
CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
CONFIG_LWIP_TCP_RECVMBOX_SIZE=10
CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
# CONFIG_LWIP_TCP_SACK_OUT is not set
# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
@@ -876,7 +857,7 @@ CONFIG_LWIP_MAX_UDP_PCBS=16
CONFIG_LWIP_UDP_RECVMBOX_SIZE=6
# end of UDP
CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=6000
CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set
@@ -1173,3 +1154,152 @@ CONFIG_WPA_MBEDTLS_CRYPTO=y
#
# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
# end of Compatibility options
# Deprecated options for backward compatibility
CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
CONFIG_LOG_BOOTLOADER_LEVEL=3
# CONFIG_APP_ROLLBACK_ENABLE is not set
# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
# CONFIG_FLASHMODE_QIO is not set
# CONFIG_FLASHMODE_QOUT is not set
CONFIG_FLASHMODE_DIO=y
# CONFIG_FLASHMODE_DOUT is not set
# CONFIG_MONITOR_BAUD_9600B is not set
# CONFIG_MONITOR_BAUD_57600B is not set
CONFIG_MONITOR_BAUD_115200B=y
# CONFIG_MONITOR_BAUD_230400B is not set
# CONFIG_MONITOR_BAUD_921600B is not set
# CONFIG_MONITOR_BAUD_2MB is not set
# CONFIG_MONITOR_BAUD_OTHER is not set
CONFIG_MONITOR_BAUD_OTHER_VAL=115200
CONFIG_MONITOR_BAUD=115200
CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set
# CONFIG_CXX_EXCEPTIONS is not set
CONFIG_STACK_CHECK_NONE=y
# CONFIG_STACK_CHECK_NORM is not set
# CONFIG_STACK_CHECK_STRONG is not set
# CONFIG_STACK_CHECK_ALL is not set
# CONFIG_WARN_WRITE_STRINGS is not set
# CONFIG_DISABLE_GCC8_WARNINGS is not set
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
CONFIG_ESP32_APPTRACE_DEST_NONE=y
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
CONFIG_ADC2_DISABLE_DAC=y
CONFIG_SPIRAM_SUPPORT=y
# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set
CONFIG_TRACEMEM_RESERVE_DRAM=0x0
# CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set
CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
# CONFIG_ULP_COPROC_ENABLED is not set
CONFIG_ULP_COPROC_RESERVE_MEM=0
CONFIG_BROWNOUT_DET=y
CONFIG_BROWNOUT_DET_LVL_SEL_0=y
# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set
CONFIG_BROWNOUT_DET_LVL=0
CONFIG_REDUCE_PHY_TX_POWER=y
CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
# CONFIG_NO_BLOBS is not set
# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
CONFIG_MAIN_TASK_STACK_SIZE=3584
CONFIG_IPC_TASK_STACK_SIZE=1024
CONFIG_TIMER_TASK_STACK_SIZE=3584
CONFIG_CONSOLE_UART_DEFAULT=y
# CONFIG_CONSOLE_UART_CUSTOM is not set
# CONFIG_CONSOLE_UART_NONE is not set
CONFIG_CONSOLE_UART_NUM=0
CONFIG_CONSOLE_UART_BAUDRATE=115200
CONFIG_INT_WDT=y
CONFIG_INT_WDT_TIMEOUT_MS=300
CONFIG_INT_WDT_CHECK_CPU1=y
CONFIG_TASK_WDT=y
# CONFIG_TASK_WDT_PANIC is not set
CONFIG_TASK_WDT_TIMEOUT_S=5
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
# CONFIG_EVENT_LOOP_PROFILING is not set
CONFIG_POST_EVENTS_FROM_ISR=y
CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
CONFIG_MB_QUEUE_LENGTH=20
CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
CONFIG_MB_SERIAL_BUF_SIZE=256
CONFIG_MB_SERIAL_TASK_PRIO=10
# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set
CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
CONFIG_MB_CONTROLLER_STACK_SIZE=4096
CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
CONFIG_MB_TIMER_PORT_ENABLED=y
CONFIG_MB_TIMER_GROUP=0
CONFIG_MB_TIMER_INDEX=0
CONFIG_SUPPORT_STATIC_ALLOCATION=y
# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
CONFIG_TIMER_TASK_PRIORITY=1
CONFIG_TIMER_TASK_STACK_DEPTH=2048
CONFIG_TIMER_QUEUE_LENGTH=10
# CONFIG_L2_TO_L3_COPY is not set
# CONFIG_USE_ONLY_LWIP_SELECT is not set
CONFIG_ESP_GRATUITOUS_ARP=y
CONFIG_GARP_TMR_INTERVAL=60
CONFIG_TCPIP_RECVMBOX_SIZE=32
CONFIG_TCP_MAXRTX=12
CONFIG_TCP_SYNMAXRTX=6
CONFIG_TCP_MSS=1440
CONFIG_TCP_MSL=60000
CONFIG_TCP_SND_BUF_DEFAULT=5744
CONFIG_TCP_WND_DEFAULT=5744
CONFIG_TCP_RECVMBOX_SIZE=10
CONFIG_TCP_QUEUE_OOSEQ=y
# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
CONFIG_TCP_OVERSIZE_MSS=y
# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
# CONFIG_TCP_OVERSIZE_DISABLE is not set
CONFIG_UDP_RECVMBOX_SIZE=6
CONFIG_TCPIP_TASK_STACK_SIZE=6000
CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
# CONFIG_PPP_SUPPORT is not set
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
CONFIG_ESP32_PTHREAD_STACK_MIN=768
CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set
# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
CONFIG_SUPPORT_TERMIOS=y
# End of deprecated options